DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
Response to Arguments
Applicant's arguments filed 6/22/2026 regarding the prior art rejections of Claims 1 - 10 have been fully considered not are not persuasive.
The Remarks argue that:
While the legitimacy of the ground for the claim objection is questioned, claims 3-5 and 13-15 have been amended, and as amended, claims 3-5 and 13-15 are submitted to be compliant. Thus, withdrawal of the foregoing objection is respectfully requested.
The Office Action admits that Varanasi fails to teach or suggest "adjusting values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage" as recited by claim 1.
Zeng cannot be reasonably interpreted as disclosing or suggesting "adjusting values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage" as recited by claim 1.
Yassine does not remedy the deficiencies in Varanasi and Zeng with respect to claim 1.
The proposed combination of Varanasi, Zeng, and Yassine fails to teach or suggest all of the features of independent claim 1. The Office Action has thus failed to establish that independent claim 1 and its dependent claims are prima facie obvious. The Examiner is therefore respectfully requested to withdraw the rejection of independent claim 1 and its dependent claims and to allow these claims.
The Examiner acknowledges claim objections for claims 3-5 & 13-15 have been corrected.
The Examiner disagrees Varanasi in view of Zeng in view of Yassine teaches "adjusting values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage" as recited by claim 1. Varanasi teaches dividing bins based on a voltage parameter. (Varanasi: 0029, This threshold splits the entire x-axis (i.e., voltage axis) into two bins: one bin—bin 1—to the left of the threshold, or all the sense voltages<0, and another bin—bin 2—to the right of the threshold defining all voltages>=0. Therefore, Y takes two values: Y={Bin 1, Bin 2} and |Y|=2.) Zeng teaches the adjusting of the LLR values for decoding of the data read from the storage. (Zeng: 0009, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1).sup.th read voltage threshold.) Yassine suggests decoding with checksum and teaches bins and adjusting LLR values too. (Yassine: 0040 & 0055, Soft decoding algorithms that can be used include, amongst others, mini-sum algorithms and Viterbi decoding. During use of the memory array (FIG. 4), the most recently stored LLRs are used for soft-decoding the read data, if the data cannot be read using hard decoding only. As memory arrays degrade with use it is important that, from time to time, the stored LLR values are updated. The process checks if a trigger condition (for example reaching a predetermined number of program/erase cycles, decoding failure or reaching a number of estimated errors that exceeds a predetermined threshold) for such an update is fulfilled and, if so, deviates from the normal read/write array operation to update LLRs. The trigger conditions include one or more of, a predetermined threshold number of program and erase cycles being reached, the number of read errors exceeding a predetermined error threshold, etc.)
One skilled in the art could combine these prior art references to conclude the limitations of the claims, maintaining the previous prior art rejection.
Claims 2 – 10 which depend from claim 1, have been considered and rejected.
Claims 12 – 20 which depend from claim 11, have been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Varanasi (US 2019/0379399 A1) in view of Zeng (US 2018/0246782 A1) in view of Yassine (US 2020/0294611 A1).
In regards to claim 1, Varanasi teaches:
A method for decoding data read from a storage of a memory system, comprising: reading the data stored in the storage of the memory system with read voltages spanning a range of voltage threshold distributions; (0022, the distribution of programmed voltages in a flash memory cell 10 can be modeled as Gaussian with the mean centered at the target program voltage. The target program voltage can be mapped for stored bit 1 to −1 and for stored bit 0 to 1. When reading the cell 10, the threshold voltage, V.sub.t (5c), is set at the midpoint between the two means—which is 0—and declare the bit stored in the cell to be ‘ 1’ or ‘0’ depending on whether the sensed voltage is below or above the threshold as shown in FIG. 1. In FIG. 1, there are two additional thresholds—shown at 5b and 5a respectively;)
Varanasi fails to teach:
and adjusting values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage.
However, Zeng teaches:
and adjusting values of the initial log likelihood ratio values for each bin to provide adjusted log likelihood ratio values for each bin prior to a final decoding of the data read from the storage. (0056,
the status of the medium particle is read again by adjusting a read voltage threshold and the original information is recovered using the error-correcting code.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes used in flash memory-based systems of Varanasi with the teaching of Zeng, which teaches a flash memory error correction method and apparatus in order to improve efficiency in the memory. (Zeng: Abstract, improving performance of an SSD storage system.)
Varanasi in view Zeng of fails to teach:
and including voltages within each of the voltage threshold distributions; dividing the range into bins spanning the range; generating initial log likelihood ratio values for each bin and generating a bin sequence of bin positions;
However, Yassine teaches:
and including voltages within each of the voltage threshold distributions; dividing the range into bins spanning the range; (0043, In FIG. 3A three read threshold voltages (indicated by the three dashed lines) are used to segment the threshold voltage range into four bins/quantization levels numbered from 0 to 3.) generating initial log likelihood ratio values for each bin and generating a bin sequence of bin positions; (0018 & 0016, The parameter may be one or more of a log likelihood ratio (LLR) associated with a quantization bin used in retrieving and/or soft decoding stored data and a transition probability associated with a quantization bin; once updates are stored, a normal operating mode in which the updated parameters are used for soft decoding stored data is switched to.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes used in flash memory-based systems of Varanasi with the teaching of Yassine, which teaches soft boundaries and log-likelihood ratio updates for flash memory in order to manage and improve errors in the memory. (Yassine: 0015, stores parameters for use in soft decoding stored data.)
In regards to claim 2, Varanasi in view of Zeng in view of Yassine teaches:
The method of claim 1, wherein the generating initial log likelihood ratio values for each bin comprises generating a channel log likelihood ratio sequence for decoding data read from the storage. (0013, generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes stored in memory)
In regards to claim 3, Varanasi in view of Zeng in view of Yassine teaches:
The method of claim 2, wherein the adjusting the log likelihood ratio values for each bin comprises: a) conducting low density parity check (LDPC) min-sum decoding with the initial log likelihood ratio values, and thereby generating an intermediate decoded sequence; b) calculating a checksum on the intermediate decoded sequence; c) if the checksum of the intermediate decoded sequence is zero, terminating decoding of the data read from the storage; d) if the checksum of the intermediate decoded sequence is not zero, generating updated log likelihood ratio values based on values in the intermediate decoded sequence; and e) using the updated log likelihood ratio values as the channel log likelihood ratio sequence for decoding of the data read from the storage. (0013, a method for generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes stored in memory, the method comprising the steps of: generating binary data in a plurality of cells stored in the memory; writing the binary data in the plurality of cells; determining hard-decisions based on a predefined hard-read voltage threshold for each of the plurality of cells; generating soft-read threshold settings; determining probabilities corresponding to each soft-read threshold setting; determining mutual information (MI) for the set of probabilities generated by the soft-read threshold settings; determining the soft-read thresholds that resulted in maximum mutual (MI) information; and generating log-likelihood-ratio (LLR) values for the LDPC for the set of soft-read thresholds that maximized the mutual information (MI).)
In regards to claim 4, Varanasi in view of Zeng in view of Yassine teaches the method of claim 3.
Varanasi fails to teach:
wherein the generating updated log likelihood ratio values comprises: calculating log likelihood ratios at a) a number of positions in the intermediate decoded sequence and the bin label sequence with pattern (0, j) and b) a number of positions in the intermediate decoded sequence and the bin label sequence with pattern (1, j).
However, Zeng teaches:
wherein the generating updated log likelihood ratio values comprises: calculating log likelihood ratios at a) a number of positions in the intermediate decoded sequence and the bin label sequence with pattern (0, j) and b) a number of positions in the intermediate decoded sequence and the bin label sequence with pattern (1, j). (0060, adjusted to a read voltage threshold option 1 (01 h) according to a sequence in Table 1 (the sequence in the table is a default read threshold adjustment sequence given by Micron, or the sequence may be defined by a user according to an actual application scenario), and perform the ECC error correction decoding; and if the decoding succeeds, the ECC decoding device resets the read voltage threshold to the default read voltage threshold (an option 0), then feeds back a decoding success state, and outputs the correct original information;)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes used in flash memory-based systems of Varanasi with the teaching of Zeng, which teaches a flash memory error correction method and apparatus in order to improve efficiency in the memory. (Zeng: Abstract, improving performance of an SSD storage system.)
In regards to claim 5, Varanasi in view of Zeng in view of Yassine teaches:
The method of claim 4, wherein the calculating a log likelihood ratio utilizes a bucket counter for counting a) the number of positions in the intermediate decoded sequence and the bin label sequence with the pattern (0, j) and b) the number of positions in the intermediate decoded sequence and the bin label sequence with the pattern (1, j). (0013, a method for generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes stored in memory, the method comprising the steps of: generating binary data in a plurality of cells stored in the memory; writing the binary data in the plurality of cells; determining hard-decisions based on a predefined hard-read voltage threshold for each of the plurality of cells; generating soft-read threshold settings;)
In regards to claim 6, Varanasi in view of Zeng in view of Yassine teaches the method of claim 1.
Varanasi fails to teach:
further comprising receiving the data to be stored in the storage, scrambling the data, then encoding the data, and thereafter storing the data in the storage.
However, Zeng teaches:
further comprising receiving the data to be stored in the storage, scrambling the data, then encoding the data, and thereafter storing the data in the storage. (0045, The write data processing module completes processing operations such as compression, encryption, scrambling, and ECC coding of a data stream. Operations performed by the read data processing module are reverse processes of that performed by the write data processing module, and the read data processing module completes processing operations such as ECC decoding, descrambling, decryption, and decompression of data read from a flash memory.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes used in flash memory-based systems of Varanasi with the teaching of Zeng, which teaches a flash memory error correction method and apparatus in order to improve efficiency in the memory. (Zeng: Abstract, improving performance of an SSD storage system.)
In regards to claim 7, Varanasi in view of Zeng in view of Yassine teaches the method of claim 1.
Varanasi fails to teach:
further comprising receiving the data to be stored in the storage, encoding the data, then scrambling the data, and thereafter storing the data in the storage.
However, Zeng teaches:
further comprising receiving the data to be stored in the storage, encoding the data, then scrambling the data, and thereafter storing the data in the storage. (0045, The write data processing module completes processing operations such as compression, encryption, scrambling, and ECC coding of a data stream. Operations performed by the read data processing module are reverse processes of that performed by the write data processing module, and the read data processing module completes processing operations such as ECC decoding, descrambling, decryption, and decompression of data read from a flash memory.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes used in flash memory-based systems of Varanasi with the teaching of Zeng, which teaches a flash memory error correction method and apparatus in order to improve efficiency in the memory. (Zeng: Abstract, improving performance of an SSD storage system.)
In regards to claim 8, Varanasi in view of Zeng in view of Yassine teaches the method of claim 7.
Varanasi fails to teach:
further comprising: flipping a sign of the initial log likelihood ratio values; decoding the data with the initial log likelihood ratio values to produce an intermediate decoded sequence, and scrambling the intermediate decoded sequence prior to the adjusting values of the initial log likelihood ratio values.
However, Zeng teaches:
further comprising: flipping a sign of the initial log likelihood ratio values; decoding the data with the initial log likelihood ratio values to produce an intermediate decoded sequence, and scrambling the intermediate decoded sequence prior to the adjusting values of the initial log likelihood ratio values. (0045, The write data processing module completes processing operations such as compression, encryption, scrambling, and ECC coding of a data stream. Operations performed by the read data processing module are reverse processes of that performed by the write data processing module, and the read data processing module completes processing operations such as ECC decoding, descrambling, decryption, and decompression of data read from a flash memory.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes used in flash memory-based systems of Varanasi with the teaching of Zeng, which teaches a flash memory error correction method and apparatus in order to improve efficiency in the memory. (Zeng: Abstract, improving performance of an SSD storage system.)
In regards to claim 9, Varanasi in view of Zeng in view of Yassine teaches the method of claim 1.
Varanasi in view Zeng of fails to teach:
wherein the adjusted log likelihood ratio values for each bin match the voltage threshold distributions.
However, Yassine teaches:
wherein the adjusted log likelihood ratio values for each bin match the voltage threshold distributions. (0012 & 0043, determines probabilities corresponding to each soft-read threshold setting; In FIG. 3A three read threshold voltages (indicated by the three dashed lines) are used to segment the threshold voltage range into four bins/quantization levels numbered from 0 to 3.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes used in flash memory-based systems of Varanasi with the teaching of Yassine, which teaches soft boundaries and log-likelihood ratio updates for flash memory in order to manage and improve errors in the memory. (Yassine: 0015, stores parameters for use in soft decoding stored data.)
In regards to claim 10, Varanasi in view of Zeng in view of Yassine teaches the method of claim 1. Varanasi in view Zeng of fails to teach:
wherein the adjusted log likelihood ratio values for each bin match the voltage threshold distributions as the storage is used over time.
However, Yassine teaches:
wherein the adjusted log likelihood ratio values for each bin match the voltage threshold distributions as the storage is used over time. (0038, the two central charge distributions (which, in this example, corresponds to a logical “1”) or to left-most or right-most charge distribution (which, in this example, corresponds to a logical “0”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a generating log-likelihood-ratio (LLR) values for low-density-parity-check (LDPC) codes used in flash memory-based systems of Varanasi with the teaching of Yassine, which teaches soft boundaries and log-likelihood ratio updates for flash memory in order to manage and improve errors in the memory. (Yassine: 0015, stores parameters for use in soft decoding stored data.)
With regards to claim 11, Varanasi in view of Zeng in view of Yassine teaches the memory system and corresponds to claim 1 as analyzed accordingly.
With regards to claim 12, Varanasi in view of Zeng in view of Yassine teaches the memory system of claim 11 and corresponds to claim 2 as analyzed accordingly.
With regards to claim 13, Varanasi in view of Zeng in view of Yassine teaches memory system of claim 12 and corresponds to claim 3 as analyzed accordingly.
With regards to claim 14, Varanasi in view of Zeng in view of Yassine teaches the memory system of claim 13 and corresponds to claim 4 as analyzed accordingly.
With regards to claim 15, Varanasi in view of Zeng in view of Yassine teaches the memory system of claim 14 and corresponds to claim 5 as analyzed accordingly.
With regards to claim 16, Varanasi in view of Zeng in view of Yassine teaches the memory system of claim 15 and corresponds to claim 6 as analyzed accordingly.
With regards to claim 17, Varanasi in view of Zeng in view of Yassine teaches the memory system of claim 15 and corresponds to claim 7 as analyzed accordingly.
With regards to claim 18, Varanasi in view of Zeng in view of Yassine teaches the memory system of claim 17 and corresponds to claim 8 as analyzed accordingly.
With regards to claim 19, Varanasi in view of Zeng in view of Yassine teaches the memory system of claim 11 and corresponds to claim 9 as analyzed accordingly.
With regards to claim 20, Varanasi in view of Zeng in view of Yassine teaches the memory system of claim 11 and corresponds to claim 10 as analyzed accordingly.
Conclusion
Applicant's arguments filed 06/10/2026 regarding the prior art rejections of Claims 1 – 20 have
been fully considered but are not persuasive.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/ Primary Examiner, Art Unit 2111
08/13/2026
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