Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 4: WL5, WL6, WL7, WL8; FIG. 5: WL5, WL6, WL7, WL8. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-7 and 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 sets forth “the second region of the diode corresponding to the anti-fuse cell that is not adjacent to the select transistor being connected to the second source/drain via the metal layer.” There is insufficient antecedent basis for this limitation in the claim. In particular, there is no previous mention in the claims to “the anti-fuse cell that is not adjacent to the select transistor”.
Paragraph [0032] of the instant specification sets forth “It should be understood that when an element or layer is referred to as being “on”, “adjacent to”, “connected to”, or “coupled to” another element or layer, the element or layer may be directly on, adjacent to, connected to, or coupled to [the] another element or layer, or there may be an element or layer in between.” This provided definition of “adjacent to” provides a broad range for what can be considered “adjacent to” as it is used in the claims. Further, this requires that if one cell and/or region is adjacent, it does not preclude any other cell and/or region from also being adjacent unless explicitly defined otherwise.
Therefore, the claim language as used in claim 3 is indefinite and cannot be made and/or used by one of ordinary skill in the art. Appropriate correction is required.
Claims 4-7 are rejected as dependent upon claim 3.
Claim 13 sets forth a programmable device array, comprising: a plurality of programmable devices according to claim 1 arranged in sequence along a second direction, wherein the gates of the select transistors arranged in a row along the second direction are connected to each other, and the second ends of the anti-fuse cells arranged in a row along the second direction are connected to each other.
There is insufficient antecedent basis for this limitation in the claim. In particular, the claim sets forth “the gates of the select transistors arranged in a row along the second direction are connected to each other”, and there is no previous mention of “the gates of the select transistors arranged in a row along the second direction”. Therefore, one of ordinary skill in the art would not be able to make and/or use the invention. Appropriate correction is required.
Claims 14-15 are rejected as dependent upon claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210350863 A1 (Liu) in view of US 20160141049 A1 (Song).
Regarding claim 1, Liu teaches a programmable device, (Liu, “anti-fuse device and a diode”; FIG. 1-6) comprising: a bit line; (Liu, [0007]: “electrically connected with a bit line”) a select transistor, (Liu, [0017]: “a selection transistor”) a first source/drain of the select transistor being electrically connected to the bit line; (Liu, [0034]: “The switch 30 may be an N-channel Metal Oxide Semiconductor (NMOS) tube. The drain electrode of the NMOS tube is connected with the bit line voltage,”). Liu does not appear to teach a select signal line, the select signal line being electrically connected to a gate of the select transistor; a plurality of diodes; a plurality of anti-fuse cells, a first end of each one of the plurality of anti-fuse cells being electrically connected to a second source/drain of the select transistor via a corresponding one of the plurality of diodes; and a plurality of word lines, each one of the plurality of word lines being electrically connected to a second end of a corresponding one of the plurality of anti-fuse cells.
Song cures the deficiencies of Liu. Song teaches a select signal line, the select signal line being electrically connected to a gate of the select transistor; (Song, FIGS. 1-6; [0033]: “The selection transistors may be used to select at least one of the unit cells during a program operation or a read operation.”) a plurality of diodes; (Song, [0068]: “first diodes D11, D12, D13, D14…”) a plurality of anti-fuse cells, (Song, [0008]: “Each of the unit cells is composed of one anti fuse transistor having a metal-oxide-semiconductor (MOS) transistor structure”) a first end of each one of the plurality of anti-fuse cells being electrically connected to a second source/drain of the select transistor via a corresponding one of the plurality of diodes; (Song, FIGS. 1-5; Song, [0042]: “A plurality of second source/ drain regions 141 b, 142 b and 143 b and a second drain region 144 b may be disposed in the second well region 130 b which is located in the second row. Although not shown in FIG. 1, sidewalls and bottom surfaces of the second source/ drain regions 141 b, 142 b and 143 b and the second drain region 144 b may be surrounded by the second well region 130 b. The second source/ drain regions 141 b, 142 b and 143 b and the second drain region 144 b may be arrayed in the first direction and may be spaced apart from each other.”) and a plurality of word lines, (Song, [0073]: “Referring to FIG. 6, the plurality of word lines WL1, WL2, WL3 and WL4 may be arrayed in the first direction”) each one of the plurality of word lines being electrically connected to a second end of a corresponding one of the plurality of anti-fuse cells. (Song, [0055]: “FIG. 2 is a cross-sectional view taken along a line I-I′ of FIG. 1. FIG. 2 illustrates cross-sectional views of first transistors T11, T12, T13 and T14 corresponding to the unit cells C11, C12, C13 and C14”).
Liu and Song are both directed to programmable devices and operation methods including the same, and both Liu and Song teach anti-fuse devices. One of ordinary skill in the art would find it obvious to combine the teachings of Song with the teachings of Liu in order to implement the programmable device as taught in claim 1 with the motivation of improving functionality of the anti-fuse programmable device by modifying the structure of Liu with the teachings of Song.
Regarding claim 2, Liu/Song teaches the device according to claim 1, wherein the plurality of diodes are disposed in a substrate (Song, [0056]: “Referring to FIGS. 1 and 2, the deep well region 120 of the first conductivity type, for example, an N-type deep well region may be disposed in an upper region of a substrate 110.”) and each one of the plurality of diodes comprises a first region disposed adjacent to one of the plurality of anti-fuse cells and a second region disposed adjacent to the first region; the second region of one of the plurality of diodes corresponding to one of the plurality of anti-fuse cells disposed adjacent to the select transistor occupies a same position as the second source/drain. (Song, FIG. 1, 2, 5; [0067-0068]: “…A gate terminal GT14 of the transistor T14 located at a cross point of the first row and the fourth column may be electrically connected to the fourth word line WL4. The drain terminal DT11 of the transistor T11 and the source terminal ST12 of the transistor T12 may be electrically connected to a cathode of a first diode D11 located at a cross point of the first row and the first column, and the drain terminal DT12 of the transistor T12 and the source terminal ST13 of the transistor T13 may be electrically connected to a cathode of a first diode D12 located at a cross point of the first row and the second column. Similarly, the drain terminal DT13 of the transistor T13 and the source terminal ST14 of the transistor T14 may be electrically connected to a cathode of a first diode D13 located at a cross point of the first row and the third column and the drain terminal DT14 of the transistor T14 may be electrically connected to a cathode of a first diode D14 located at a cross point of the first row and the fourth column. Anodes of the first diodes D11, D12, D13 and D14 may be electrically connected to the first well bias line PWL1. The anodes of the first diodes D11, D12, D13 and D14 may also be electrically connected to an anode of a deep well diode DN. A cathode of the deep well diode DN may be electrically connected to the deep well bias line NWL.”)
Regarding the claim language “adjacent to”, the instant specification provides in [0032]: “It should be understood that when an element or layer is referred to as being “on”, “adjacent to”, “connected to”, or “coupled to” another element or layer, the element or layer may be directly on, adjacent to, connected to, or coupled to [the] another element or layer, or there may be an element or layer in between.” Additionally, regarding the claim language “same position”, this limitation is not clarified in the instant specification, and is given its broadest reasonable interpretation in the claims.
Regarding claim 8, Liu/Song teaches the device according to claim 1, wherein the plurality of diodes are disposed in a substrate, (Song, [0056]: “Referring to FIGS. 1 and 2, the deep well region 120 of the first conductivity type, for example, an N-type deep well region may be disposed in an upper region of a substrate 110.”) each one of the plurality of diodes comprises a first region and a second region, the first region is electrically connected to the first end, the second region is electrically connected to the second source/drain. (Song, FIG. 1, 2, 5; [0067-0068]: “…A gate terminal GT14 of the transistor T14 located at a cross point of the first row and the fourth column may be electrically connected to the fourth word line WL4. The drain terminal DT11 of the transistor T11 and the source terminal ST12 of the transistor T12 may be electrically connected to a cathode of a first diode D11 located at a cross point of the first row and the first column, and the drain terminal DT12 of the transistor T12 and the source terminal ST13 of the transistor T13 may be electrically connected to a cathode of a first diode D12 located at a cross point of the first row and the second column. Similarly, the drain terminal DT13 of the transistor T13 and the source terminal ST14 of the transistor T14 may be electrically connected to a cathode of a first diode D13 located at a cross point of the first row and the third column and the drain terminal DT14 of the transistor T14 may be electrically connected to a cathode of a first diode D14 located at a cross point of the first row and the fourth column. Anodes of the first diodes D11, D12, D13 and D14 may be electrically connected to the first well bias line PWL1. The anodes of the first diodes D11, D12, D13 and D14 may also be electrically connected to an anode of a deep well diode DN. A cathode of the deep well diode DN may be electrically connected to the deep well bias line NWL.”)
Regarding claim 9, Liu/Song teaches the device according to claim 8, wherein the second region and the second source/drain overlay in the substrate. (Song, FIG. 1, 2, 5; [0067-0068]; no definition is provided for “overlay” in the instant specification, and the term is given its broadest reasonable interpretation; generally the term is understood as “cover the surface of something”).
Regarding claim 10, Liu/Song teaches the device according to claim 8, wherein the second region and the second source/drain are P-type doped, and the first region is N-type doped. (Liu/Song provides for any reasonable arrangement of P-type and N-type doping, and provides such examples: (Song, [0038]: “Referring to FIG. 1, the anti-fuse type OTP memory cell array 100 may include a plurality of well regions 130 a, 130 b, 130 c and 130 d. Sidewalls and bottom surfaces of the well regions 130 a, 130 b, 130 c and 130 d may be surrounded by a deep well region 120. The deep well region 120 may have a first conductivity type, and the well regions 130 a, 130 b, 130 c and 130 d may have a second conductivity type which is opposite to the first conductivity type. In the present embodiment, the deep well region 120 may be N-type and the well regions 130 a, 130 b, 130 c and 130 d may be P-type. Alternatively, the deep well region 120 may be P-type and the well regions 130 a, 130 b, 130 c and 130 d may be N-type. The deep well region 120 may be formed by performing an ion implantation process with a mask pattern and a diffusion process. Similarly, the well regions 130 a, 130 b, 130 c and 130 d may also be formed by performing an ion implantation process with a mask pattern and a diffusion process…”))
Regarding claim 11, Liu/Song teaches the device according to claim 8, further comprising a metal layer, wherein the second region is electrically connected to the second source/drain via the metal layer. (Liu, [0025]: “A material of the gate layer 103 may be at least one of polycrystalline silicon, titanium, tungsten, a metal silicide or other conductive materials. However, the material of the gate layer 103 cannot be limited to this in an actual embodiment.”)
It would be obvious to one of ordinary skill in the art to combine the additional gate layer 103 of Liu with the configuration of regions as taught in Song in order to teach the metal layer of claim 11, with the motivation of attempting to improve functionality of the device.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210350863 A1 (Liu) in view of US 20160141049 A1 (Song) in view of US 20230061128 (Yang).
Regarding claim 12, Liu/Song teaches the device according to claim 11, but does not teach further comprising a first conductive pillar, wherein the second region is connected to the metal layer via the first conductive pillar.
Yang cures the deficiencies of Liu/Song. Yang teaches further comprising a first conductive pillar, wherein the second region is connected to the metal layer via the first conductive pillar. (Yang, [0006]: “An embodiment of the disclosure provides a method of fabricating a memory device, including the following steps. A metal interconnect structure is formed on a substrate. A first stack structure is formed on the metal interconnect structure, and the first stack structure includes a plurality of first conductive layers and a plurality of first insulating layers that alternate with each other. An insulating structure is formed in the first stack structure. A first conductive pillar is formed in the insulating structure. A second stack structure is formed on the first stack structure, the insulating structure, and the first conductive pillar, and the second stack structure includes a plurality of second insulating layers and a plurality of middle layers that alternate with each other. A first contact is formed to pass through the second insulating layers and the middle layers of the second stack structure to be electrically connected to the first conductive pillar.”)
Liu/Song and Yang are both directed to programmable devices and memory devices. It would be obvious to one of ordinary skill in the art to modify the teachings of Liu/Song with the arrangement of conductive pillars of Yang with the motivation of improving functionality of the memory device.
Regarding claims 3-7 and 13-15, resolution of indefiniteness issues are required before an indication of allowable subject matter can be made. Further search and consideration is required upon resolution of indefiniteness issues.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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