DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10, 14, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Devoe et al. (US 6,366,443).
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Regarding claim 1, Devoe et al. disclose in Fig. 3a-3c, a multilayer electronic component, comprising:
a plurality of dielectric layers (see annotated figure 3b above) stacked in a Z-direction (see annotated figure 3b above) that is perpendicular to each of an X-direction (see annotated figure 3c above) and a Y-direction (see annotated figure 3c), the X-direction perpendicular to the Y-direction (see annotated figure 3c), the plurality of dielectric layers comprising a dielectric material (ceramic);
a first conductive layer (14a) overlying one of the plurality of dielectric layers;
a second conductive layer (14b) overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer (14a) in the Z-direction, the second conductive layer (14b) overlapping the first conductive layer (14a) in each of the X-direction and the Y-direction at an overlapping area to form a capacitor (see annotated figure 3c above); and
a first via (13a) connected with the first conductive layer (14a) at a first location outside of the overlapping area (see annotated figure 3c above).
Regarding claim 2, Devoe et al. disclose a second via (13b) connected with the second conductive layer (14b) at a second location outside of the overlapping area (see annotated figure 3c above).
Regarding claim 3, Devoe et al. disclose the first location (@ 13a) is offset from the second location (@13b) along at least one of the X-direction or the Y-direction (see annotated figure 3c above).
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Regarding claim 4, Devoe et al. disclose the first conductive layer (14a) includes a first section (see annotated figure 3c above) that defines the first location and the second conductive layer (14b) includes a second section (see annotated figure 3c above) that defines the second location, and wherein the first section and the second section are spaced apart from one another along the X-direction and the Y-direction.
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Regarding claim 5, Devoe et al. disclose the first location (@13a) and the second location (@13b) are spaced apart by a spacing distance in the X-direction, and wherein the overlapping area has a length in the X-direction that is less than the spacing distance (see annotated figure 3 above).
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Regarding claim 6, Devoe et al. disclose the first location (@13a) and the second location (@13b) are spaced apart by a spacing distance in the X-direction, and wherein the overlapping area has a length in the X-direction that is greater than the spacing distance (see annotated figure. 3c above).
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Regarding claim 7, Devoe et al. disclose the first location (@13a) and the second location (@13b) are spaced apart by a spacing distance in the Y-direction, and wherein the overlapping area has a width in the Y-direction that is greater than the spacing distance.
Regarding claim 8, Devoe et al. disclose the overlapping area comprises a first side (left) and a second (right) side opposite the first side along the X-direction, and wherein the first location (@13a) is defined adjacent the first side (left) and the second location (@13b) is defined adjacent the second side (right).
Regarding claim 9, Devoe et al. disclose the overlapping area comprises a first side (left) and a second side (right) opposite the first side along the X-direction (let-right – Fig. 3c), and wherein both the first location (@13a) and the second location (@13b) are defined adjacent one of the first side or the second side, the first location (@13a) and the second location (@13b) spaced apart from one another along the Y-direction (top-bottom – Fig. 3c).
Regarding claim 10, Devoe et al. disclose the overlapping area comprises a third side (top) and a fourth side (bottom) opposite the third side along the Y-direction (top-bottom – Fig. 3c), and wherein the first location (@13a) is defined adjacent the third side (top) and the second location (@13b) is defined adjacent the fourth side (bottom).
Regarding claim 14, Devoe et al. disclose the dielectric material is disposed between the first conductive layer (14a) and the second conductive layer (14b).
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Regarding claim 17, Devoe et al. disclose a method of forming a multilayer electronic component, the method comprising:
providing a plurality of dielectric layers (see annotated figure above);
forming a first conductive layer (14a) overlying one of the plurality of dielectric layers;
forming a second conductive layer (14b) overlying another of the plurality of dielectric layers (see annotated figure above) and spaced apart from the first conductive layer (14a) in a Z-direction;
stacking the plurality of dielectric layers such that the first conductive layer (14a)
overlaps the second conductive layer (14b) in each of an X-direction and a Y-direction at an overlapping area to form a capacitor,
the X-direction perpendicular to the Y-direction and each of the X-direction and the Y-direction perpendicular to the Z-direction (see annotated figure above); and
forming a first via (13a) connected with the first conductive layer (14a) at a first location outside of the overlapping area.
Regarding claim 18, Devoe et al. disclose forming a second via (13b) connected with the second conductive layer (14b) at a second location outside of the overlapping area.
Claim(s) 1-2, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahiko et al. (US 2002/0041006 A1).
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Regarding claim 1, Ahiko et al. disclose in Fig. 4, a multilayer electronic component (1), comprising:
a plurality of dielectric layers (12) stacked in a Z-direction (Z) that is perpendicular to each of an X-direction (X) and a Y-direction (Y), the X-direction perpendicular to the Y-direction, the plurality of dielectric layers comprising a dielectric material [0049];
a first conductive layer (14) overlying one of the plurality of dielectric layers;
a second conductive layer (16) overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer (14) in the Z-direction (Z), the second conductive layer (16) overlapping the first conductive layer (14) in each of the X-direction (X) and the Y-direction (Y) at an overlapping area to form a capacitor; and
a first via (18) connected with the first conductive layer (14) at a first location outside of the overlapping area (32).
Regarding claim 2, Ahiko et al. disclose a second via (20) connected with the second conductive layer (16) at a second location outside of the overlapping area.
Regarding claim 11, Ahiko et al. disclose the overlapping area comprises a third side (front) and a fourth side (back) opposite the third side along the Y-direction (Y), and wherein both the first location (@ 18) and the second location (@ 20) are defined adjacent one of the third side (front) or the fourth side, the first location (@18) and the second location (@20) spaced apart from one another along the X-direction (X).
Claim(s) 1, 12-13, 17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ritter et al. (US 2009/0002921 A1).
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Regarding claim 1, Ritter et al. disclose in Fig. 4, a multilayer electronic component, comprising:
a plurality of dielectric layers (16) stacked in a Z-direction (top-bottom - Fig. 4) that is perpendicular to each of an X-direction (left-right – Fig. 4) and a Y-direction (front – back - Fig. 4), the X-direction perpendicular to the Y-direction, the plurality of dielectric layers comprising a dielectric material [0092];
a first conductive layer (14) overlying one of the plurality of dielectric layers (14);
a second conductive layer (12) overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer (14) in the Z-direction (top-bottom), the second conductive layer (14) overlapping the first conductive layer (12) in each of the X-direction and the Y-direction at an overlapping area (12, 14) to form a capacitor; and
a first via (44b) connected with the first conductive layer (14) at a first location outside of the overlapping area.
Regarding claim 12, Horie et al. disclose a non-conductive region (see annotated figure above) surrounded by the second conductive layer (12), the non-conductive region defined opposite the first location along the Z-direction.
Regarding claim 17, Ritter et al. disclose a method of forming a multilayer electronic component, the method comprising:
providing a plurality of dielectric layers (16);
forming a first conductive layer (14) overlying one of the plurality of dielectric layers (14);
forming a second conductive layer (12) overlying another of the plurality of dielectric layers (14) and spaced apart from the first conductive layer (14) in a Z-direction;
stacking the plurality of dielectric layers such that the first conductive layer (16)
overlaps the second conductive layer (12) in each of an X-direction and a Y-direction at an overlapping area to form a capacitor,
the X-direction perpendicular to the Y-direction and each of the X-direction and the Y-direction perpendicular to the Z-direction; and
forming a first via (44b) connected with the first conductive layer (14) at a first location outside of the overlapping area.
Regarding claim 19, Ritter et al. disclose forming a non-conductive region (see annotated figure above) surrounded by the second conductive layer (12), the non-conductive region defined opposite the first location along the Z-direction.
Regarding claim 20, Ritter et al. disclose a multilayer electronic component, comprising:
a plurality of dielectric layers (16) stacked in a Z-direction that is perpendicular to each of an X-direction and a Y-direction, the X-direction perpendicular to the Y-direction,
the plurality of dielectric layers (16) comprising a dielectric material [0092];
a first conductive layer (14) overlying a first dielectric layer (16) of the plurality of dielectric layers (16);
a second conductive layer (12) overlying a second dielectric layer (16) of the plurality of dielectric layers and spaced apart from the first conductive layer (14) in the Z-direction, the second conductive layer (12) overlapping the first conductive layer (14) in each of the X-direction and the Y-direction at an overlapping area to form a capacitor;
a via (44b) connected with the first conductive layer (14b); and
a non-conductive region (see annotated figure above) defined on the second dielectric layer such that the second conductive layer surrounds the non-conductive region,
wherein the via (44b) connects with the first conductive layer (14) at a location opposite the non-conductive region along the Z-direction.
Claim(s) 1, 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (KR 20160004231 A).
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Regarding claim 1, Choi et al. disclose in Fig. 8, a multilayer electronic component, comprising:
a plurality of dielectric layers (750-760) stacked in a Z-direction (top-bottom - Fig. 8) that is perpendicular to each of an X-direction (left-right – Fig. 8) and a Y-direction (front – back - Fig. 8), the X-direction perpendicular to the Y-direction, the plurality of dielectric layers comprising a dielectric material;
a first conductive layer (740) overlying one of the plurality of dielectric layers (770);
a second conductive layer (730) overlying another of the plurality of dielectric layers (760) and spaced apart from the first conductive layer (740) in the Z-direction (top-bottom), the second conductive layer (730) overlapping the first conductive layer (740) in each of the X-direction and the Y-direction at an overlapping area to form a capacitor; and
a first via (712) connected with the first conductive layer (740) at a first location outside of the overlapping area.
Regarding claim 14, Choi et al. disclose the dielectric material (760) is disposed between the first conductive layer (740) and the second conductive layer (730).
Regarding claim 15, Choi et al. disclose the dielectric material (760) is an organic dielectric material (Translation P: 6 P: 13).
Claim(s) 13 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Ritter et al. (US 2009/0002921 A1).
Regarding claim 13, Ritter et al. illustrate the non-conductive region has an area that is at least two times a cross-sectional area of the first via.
Ritter et al. do not specifically state that the non-conductive region has an area that is at least two times a cross-sectional area of the first via.
It is known in the art that adequate separation between a via of one polarity and a conductive region of opposite polarity ensures reliable electrical isolation between them.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the device of Ritter et al. so that the non-conductive region has an area that is at least two times a cross-sectional area of the first via, since such a modification would ensure adequate separation between the via and the second conductive layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (KR 20160004231 A).
Regarding claim 16, Choi et al. disclose the claimed invention except for the organic dielectric material comprises at least one of liquid crystalline polymer or polyphenyl ether.
LCP and polyphenyl ether are well known organic dielectric materials.
Lacking unexpected results, it would have been obvious to a person of ordinary skill in the organic dielectric material art to form the organic dielectric material comprises at least one of liquid crystalline polymer or polyphenyl ether, since insulator materials are selected based on design considerations and tradeoffs between cost, mechanical properties, and dielectric properties.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 3,195,027 A– multilayer ceramic capacitor having via connectors
US 5,590,017 A– multilayer ceramic capacitor having via connectors
US 5,774,326 A – multilayer ceramic capacitor having via connectors
US 5,876,538 A – single layer capacitor having vias
JP H07-326536 A – multilayer ceramic capacitor having via connectors
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/ERIC W THOMAS/Primary Examiner, Art Unit 2847
ERIC THOMAS
Primary Examiner
Art Unit 2847
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