Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over LEE et al. (Patent NO KR 101227744 (B1); hereinafter Lee; translation attached) in view of KIM et al. (Pub NO. US 2022/0018897 A1; hereinafter Kim).
Regarding Claim 1, Lee teaches a semiconductor test apparatus (apparatus in Fig. 1-Fig.3) comprising:
a tray housing (tray housing 1000 in Fig. 1; See [0028]-[0029]) including a loading stacker (loading stacker 100 in fig. 1 and Fig. below; See [0028]-[0029]),
a first unloading stacker (342 in fig. 3 and Fig. below; See [0064]), and
a second unloading stacker (322 in fig. 3 and Fig. below; See [0064]),
the loading stacker configured to receive a plurality of semiconductor chips for testing (See [0029]-[0030]),
the first unloading stacker configured to receive any defective semiconductor chips among the plurality of semiconductor chips (See [0064]), and
the second unloading stacker configured to receive any good semiconductor chips among the plurality of semiconductor chips (See [0064]);
a loader (372 in Fig.3 and Fig. below; See [0065]-[0067]) configured to place, on a loading set plate (set plate 374 in Fig. 3; See [0064]-[0070]), the plurality of semiconductor chips for testing, and load the plurality of semiconductor chips for testing onto a test tray (test tray CT2; See [0064]-[0067]);
a test device (10 in fig. 1; See [0029]) configured to test the plurality of semiconductor chips for testing stacked on the test tray (See [0065]-[0070]);
an unloader (370 in fig. 3 and Fig. below; See [0064]) configured to classify the plurality of tested semiconductor chips into the any defective semiconductor chip and the any good semiconductor chip based on results of the testing (See [0064]),
place the any defective semiconductor chip on the first unloading stacker (See [0064], [0077]-[0082]), and
place the any good semiconductor chip onto the second unloading stacker (See [0064], [0077]-[0082]); and
processing circuitry (test process is performed by processing circuitry; See [0037]) configured to,
to transfer the any defective semiconductor chip from the first unloading stacker to the loading set plate (See [0006], [0064]-[0070], [0077]-[0082]),
to provide at least one additional semiconductor chip to the loading stacker, and instruct the test device to retest the any defective semiconductor chip (See [0006], [0064]-[0070], [0077]-[0082]).
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Lee is silent about cause at least one robot to transfer semiconductor chip, and cause at least one robot to transfer to provide semiconductor chip.
Kim teaches cause at least one robot to transfer semiconductor chip, and cause at least one robot to transfer to provide semiconductor chip (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using to cause at least one robot to transfer semiconductor chip, and cause at least one robot to transfer to provide semiconductor chip, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 2, Lee in view of Kim teaches the semiconductor test apparatus of claim 1. Lee further teaches wherein the processing circuitry is further configured to: cause to transfer the any defective semiconductor chip to the loading set plate (loading set plate 374; See [0064]-[0070]) without passing through the first loading stacker (not passing through 100 in fig. 1; See [0064]).
Lee is silent about cause the at least one robot to transfer.
Kim teaches cause at least one robot to transfer semiconductor chip (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using to cause at least one robot to transfer semiconductor chip, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 3, Lee in view of Kim teaches the semiconductor test apparatus of claim 2. Lee further teaches wherein the loader is further configured to: load the any defective semiconductor chip onto the test tray from the loading set plate (See [0067]).
Regarding Claim 4, Lee in view of Kim teaches the semiconductor test apparatus of claim 1. Lee further teaches wherein the processing circuitry is further configured to: cause to provide the at least one additional semiconductor chip to the loading stacker in response to all of the plurality of semiconductor chips to be tested to be located on the loading set plate (See [0060]-[0065]).
Lee is silent about the at least one robot to provide the at least one additional semiconductor chip.
Kim teaches at least one robot to provide the at least one additional semiconductor chip (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using at least one robot to provide the at least one additional semiconductor chip, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 5, Lee in view of Kim teaches the semiconductor test apparatus of claim 1. Lee further teaches wherein the processing circuitry is further configured to: to provide the at least one additional semiconductor chip to the loading stacker while the plurality of semiconductor chips to be tested are tested by the test device (See [0072]-[0075]).
Lee is silent about cause the at least one robot to provide the at least one additional semiconductor.
Kim teaches cause the at least one robot to provide the at least one additional semiconductor (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using cause the at least one robot to provide the at least one additional semiconductor, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 6, Lee in view of Kim teaches the semiconductor test apparatus of claim 1. Lee further teaches wherein the processing circuitry is configured to: to provide the additional semiconductor chip to the loading stacker while the defective semiconductor chip is retested by the test device (See [0062]-[0065]).
Lee is silent about cause the at least one robot to provide the additional semiconductor chip.
Kim teaches cause the at least one robot to provide the additional semiconductor chip (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using cause the at least one robot to provide the additional semiconductor chip, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 7, Lee in view of Kim teaches the semiconductor test apparatus of claim 1. Lee further teaches wherein the loading stacker (100 in Fig. 1; See [0029]) comprises: a first loading stacker (110 in Fig. 1; See [0029]-0032]) and a second loading stacker (120 in Fig. 1; See [0029]-0032]); the first loading stacker configured to stack a first lot comprising a subset of the plurality of semiconductor chips to be tested (See [0029]-0032]); and the second loading stacker configured to stack a second lot comprising a remaining subset of the plurality of semiconductor chips to be tested (See [0029]-0032]).
Regarding Claim 8, Lee in view of Kim teaches the semiconductor test apparatus of claim 1, wherein the test tray (CT1 in Fig. 1; See [0030]) is configured to: sequentially circulate between the loader, the test device, and the unloader (See [0029]-[0032]).
Regarding Claim 9, Lee in view of Kim teaches the semiconductor test apparatus of claim 1, wherein the unloader (370 in fig. 3; See [0065]-[0070]) comprises: a first unloading set plate (372 in Fig. 3; See [0065]-[0070]) configured to receive the any defective semiconductor chip (374 in Fig. 3; See [0065]-[0070]); and a second unloading set plate (See [0065]-[0070]) configured to receive the any good semiconductor chip (See [0065]-[0070]).
Regarding Claim 10, Lee in view of Kim teaches the semiconductor test apparatus of claim 1. Lee further teaches wherein the test device comprises: a soak chamber (210; See [0035]) configured to preheat at least one semiconductor chip of the plurality of semiconductor chips to be tested (See [0035]); a test chamber configured (220) to conduct at least one test on the at least one preheated semiconductor chip (See [0035]-[0037]); and a desoak chamber (230; See [0037]) configured to change a temperature of the at least one tested semiconductor chip to room temperature (See [0037]).
Regarding Claim 11, Lee in view of Kim teaches the semiconductor test apparatus of claim 1. Lee further teaches wherein the processing circuitry is further configured to: detect whether the loading set plate is empty (See [0056], [0078]); and to transfer the any defective semiconductor chip from the first unloading stacker to the loading set plate in response to results of the detection (See [0056], [0078]).
Lee is silent about cause the at least one robot to transfer the any defective semiconductor chip.
Kim teaches cause the at least one robot to transfer the any defective semiconductor chip (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using c cause the at least one robot to transfer the any defective semiconductor chip, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 12, Lee in view of Kim teaches the semiconductor test apparatus of claim 11, wherein the processing circuitry is further configured to: start operating in response to the any defective semiconductor chip being transferred to the first unloading stacker (See [0021], [0077]-[0082]); and stop operating in response to the transfer of the any defective semiconductor chip from the first unloading stacker to the test tray being completed (stop operating any BSD device is completed; See [0077]-[0082).
Regarding Claim 13, Lee teaches a semiconductor test apparatus (apparatus in Fig. 1-Fig.3) comprising:
a tray housing (tray housing 1000 in Fig. 1; See [0028]-[0029]) including a first loading stacker (110 in Fig. 1; See [0029]-0032]) and a second loading stacker (120 in Fig. 1; See [0029]-0032]), the first loading stacker configured to receive a first lot of semiconductor chips (See [0029]-0032]), and the second loading stacker configured to receive a second lot of semiconductor chips (See [0029]-0032]);
a loader (372 in Fig.3 and Fig. below; See [0065]-[0067]) configured to transfer the first lot from the tray housing to a loading set plate (set plate 374 in Fig. 3; See [0064]-[0070]), and transfer the first lot from the loading set plate to a test tray (test tray CT2; See [0064]-[0067]);
a test device (10 in fig. 1; See [0029]) configured to test the semiconductor chips of the first lot on the test tray (See [0065]-[0070]);
an unloader (370 in fig. 3 and Fig. below; See [0064]) configured to classify the semiconductor chips of the first lot into any defective semiconductor chips among the semiconductor chips and any good semiconductor chips among the semiconductor chips based on results of the testing (See [0064]),
transfer the any defective semiconductor chip to a first unloading set plate (See [0064]), and transfer the any good semiconductor chip to a second unloading set plate (See [0064]); and
processing circuitry (test process is performed by processing circuitry; See [0037]) configured to,
to transfer the any defective semiconductor chip from the first unloading set plate to the loading set plate (See [0006], [0064]-[0070], [0077]-[0082]),
to transfer the any good semiconductor chip from the second unloading set plate to an unloading stacker (See [0006], [0064]-[0070], [0077]-[0082]),
to transfer an additional lot to the first loading stacker, and instruct the test device to retest the any defective semiconductor chip on the loading set plate (See [0006], [0064]-[0070], [0077]-[0082]).
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Lee is silent about cause at least one robot to transfer semiconductor chip.
Kim teaches cause at least one robot to transfer semiconductor chip (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using to cause at least one robot to transfer semiconductor chip, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 14, Lee in view of Kim teaches the semiconductor test apparatus of claim 13. Lee further teaches wherein the processing circuitry is further configured to: to transfer the any defective semiconductor chip to the loading set plate (loading set plate 374; See [0064]-[0070]) without passing through the first loading stacker (not passing through 100 in fig. 1; See [0064]).
Lee is silent about cause the at least one robot to transfer.
Kim teaches cause at least one robot to transfer semiconductor chip (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using to cause at least one robot to transfer semiconductor chip, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 15, Lee in view of Kim teaches the semiconductor test apparatus of claim 13. Lee further teaches wherein the processing circuitry is further configured to: to combine the second lot of semiconductor chips on the second loading stacker with the first lot of semiconductor chips on the first loading stacker (See [0050]-[0070]).
Lee is silent about cause the at least one robot to combine semiconductor chips.
Kim teaches cause the at least one robot to combine semiconductor chips (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using cause the at least one robot to combine semiconductor chips, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 16, Lee in view of Kim teaches the semiconductor test apparatus of claim 13. Lee further teaches wherein the processing circuitry is further configured to: to transfer the additional lot to the first loading stacker in response to the first lot of semiconductor chips being transferred to the loading set plate (See [0072]-[0075]).
Lee is silent about cause the at least one robot to transfer additional semiconductor.
Kim teaches cause the at least one robot to transfer additional semiconductor (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using cause the at least one robot to transfer additional semiconductor, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 17, Lee in view of Kim teaches the semiconductor test apparatus of claim 13. Lee further teaches wherein the processing circuitry is further configured to: to transfer the additional lot to the first loading stacker while the first lot is tested by the test device (See [0062]-[0065]).
Lee is silent about cause the at least one robot to transfer additional semiconductor.
Kim teaches cause the at least one robot to transfer additional semiconductor (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using cause the at least one robot to transfer additional semiconductor, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 18, Lee in view of Kim teaches the semiconductor test apparatus of claim 13. Lee further teaches wherein the processing circuitry is further configured to: to transfer the additional lot to the first loading stacker while the defective semiconductor chip is retested by the test device (374 in Fig. 3; See [0065]-[0070], [0077]-[0082]).
Lee is silent about cause the at least one robot to transfer additional semiconductor.
Kim teaches cause the at least one robot to transfer additional semiconductor (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using cause the at least one robot to transfer additional semiconductor, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Regarding Claim 19, Lee in view of Kim teaches the semiconductor test apparatus of claim 13. Lee further teaches wherein the first lot stacked on the first loading stacker (110 in Fig. 1; See [0029]-0032]) and the second lot stacked on the second loading stacker (120 in Fig. 1; See [0029]-0032]) each comprise a plurality of semiconductor chips to be tested (See [0050]-[0082]).
Regarding Claim 20, Lee teaches a semiconductor test apparatus (apparatus in Fig. 1-Fig.3) comprising:
a tray housing (tray housing 1000 in Fig. 1; See [0028]-[0029]) including
a first loading stacker (110 in Fig. 1; See [0029]-[0050]),
a second loading stacker (120 in Fig. 1; See [0029]-[0050]),
a first unloading stacker (342 in fig. 3 and Fig. below; See [0064]), and
a second unloading stacker (322 in fig. 3 and Fig. below; See [0064]),
the first loading stacker configured to receive a first lot of semiconductor chips (See [0029]-[0030]),
the second loading stacker configured to receive a second lot of semiconductor chips (See [0029]-[0030]),
the first unloading stacker configured to receive any defective semiconductor chip among the first lot (See [0064], [0077]-[0082]), and
the second unloading stacker configured to receive any good semiconductor chip among the first lot (See [0064], [0077]-[0082]);
a loader (372 in Fig.3 and Fig. below; See [0065]-[0067]) configured to transfer the first lot from the tray housing to a test tray (test tray CT2; See [0064]-[0067], [0077]-[0082]);
a test device (10 in fig. 1; See [0029]) including a soak chamber (210; See [0035]),
a test chamber (220), and
a desoak chamber (230; See [0037]), the soak chamber configured to preheat the first lot, the test chamber configured to conduct a test on each of the semiconductor chips of the first lot (See [0037]), and
the desoak chamber (230; See [0037]) configured to change a temperature of the tested semiconductor chips of the first lot to room temperature (See [0037]);
an unloader (370 in fig. 3 and Fig. below; See [0064]) configured to classify the semiconductors of the first lot into the any defective semiconductor chip and the any good semiconductor chip based on results of the testing (See [0064]),
transfer the any defective semiconductor chip to the first unloading stacker (See [0064]), and
transfer the any good semiconductor chip to the second unloading stacker (See [0064]); and
processing circuitry (test process is performed by processing circuitry; See [0037]) configured to,
to transfer the any defective semiconductor chip to a loading set plate without passing through the loading stacker (See [0006], [0064]-[0070]),
to transfer an additional semiconductor chip to the loading stacker, and instruct the test device to retest the any defective semiconductor chip (See [0006], [0064]-[0070]).
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Lee is silent about cause at least one robot to transfer semiconductor chip.
Kim teaches cause at least one robot to transfer semiconductor chip (See abstract, [0009], [0011]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Lee by using to cause at least one robot to transfer semiconductor chip, as taught by Kim in order to achieve efficient semiconductor testing (Kim; abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LEE et al. (Pub NO. US 2017/0102427 A1) discloses Semiconductor Test Apparatus.
KIMURA et al. (Pub NO. US 2016/0190020 A1) discloses Semiconductor Inspection Method.
CHEN et al. (Pub NO. US 2010/0166535 A1) discloses System and Method for Separating Defective Semiconductor Dies from Wafer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rodak Lee can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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