DETAILED ACTION
Claims 1-20 are present for examination.
Claims 1, 4-5, 8, 11-12 and 16 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 8-10, 13-14, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keil et al. (US 12,346,566) in view of Shen et al. (US 11,755,246).
With respect to claim 1, Keil et al. teaches receiving a plurality of bit strings to be written to respective memory banks of a memory device (see column 4, lines 1-5; column 8, lines 27-35 and column 10, lines 11-16; memory control circuit 101 is configured to receive write requests 105 for memory ranks 102A and 102B. In various embodiments, write requests 105 includes a first subset of write requests to memory rank 102A, and a second subset of write requests to memory rank 102B);
writing a first bit string among the plurality of bit strings to a first rank of a first memory bank among the plurality of memory banks during a first timing period (see column 10, lines 41-47; sending, by the memory control circuit, write requests allocated to the first set of slots to the first memory rank during the first write turn (block 704)); and
writing a second bit string among the plurality of bit strings to a second rank of the first memory bank among the plurality of memory banks during a second timing period (see column 10, lines 48-55; in response to completing sending the write requests allocated to the first set of slots to the first memory rank, performing, by the memory control circuit, a rank switch (block 705). The method also includes sending, by the memory control circuit, write requests allocated to the second set of slots to the second memory rank in response to completing the rank switch).
Keil does not teach wherein the first timing period is a first clock cycle and the second timing period is a second clock cycle that is sequential to the first clock cycle.
However, Shen et al. teaches wherein in a first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (i.e., write accesses between ranks are sequential) (see column 10, lines 52-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67)
With respect to claim 2, Keil does not teach writing the first bit string to the first rank of the first memory bank and writing of the second bit string to the second rank of the first memory bank prior to writing an intervening bit string to a second memory bank.
However, Shen et al. teaches arbiter 238 implements a preference for accesses to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank (i.e., write to one bank is completed before write to a different bank) (column 7, lines 1-8). In burst of write accesses 511, a write access labeled “W.sub.0” is a write access to rank 0 and a write access labeled “W.sub.1” is a write access to rank 1... Thus, in the example shown in first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (see column 10, lines 45-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67)
With respect to claim 3, Keil et al. teaches performing an arbitration operation using an arbitration circuit coupled to the memory device to control the writing of the first bit string to the first rank of the first memory bank and the writing of the second bit string to the second rank of the first memory bank (see column 4, lines 10-15 and column 5, lines 58-61; allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A... Arbitration circuit 305 is configured to allocate a particular write request to a corresponding slot. Also in column 6, lines 4-23; Arbitration circuit 305 may, in various embodiments, be configured to select the initial memory rank according to one of various operating modes… arbitration circuit 305 may use a weight function to select the initial memory rank (i.e., an order of selecting ranks is determined)).
Keil does not teach writing of the first bit string to the first rank of the first memory bank and the writing of the second bit string to the second rank of the first memory bank prior to writing an intervening bit string to a second memory bank
However, Shen et al. teaches arbiter 238 implements a preference for accesses to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank (i.e., write to one bank is completed before starting to write to a different bank) (column 7, lines 1-8). In burst of write accesses 511, a write access labeled “W.sub.0” is a write access to rank 0 and a write access labeled “W.sub.1” is a write access to rank 1... Thus, in the example shown in first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (see column 10, lines 45-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67).
With respect to claim 4, Keil et al. teaches writing a third bit string among the plurality of bit strings to a first rank of a memory bank among the plurality of memory banks during a second timing period (see column 10, lines 41-47; sending, by the memory control circuit, write requests allocated to the first set of slots to the first memory rank during the first write turn (block 704)); and
writing a fourth bit string among the plurality of bit strings to a second rank of the second memory bank among the plurality of memory banks during the second timing period (see column 10, lines 48-55; in response to completing sending the write requests allocated to the first set of slots to the first memory rank, performing, by the memory control circuit, a rank switch (block 705). The method also includes sending, by the memory control circuit, write requests allocated to the second set of slots to the second memory rank in response to completing the rank switch).
Keil et al. does not explicitly teach writing a third bit string among the plurality of bit strings to a first rank of a second memory bank, and writing a fourth bit string among the plurality of bit strings to a second rank of the second memory bank, and writing the third bit string and the fourth bit string to the first and second ranks of the second memory bank subsequent to writing the first bit string and the second bit string to the first and second ranks of the first memory bank.
However, Shen et al. teaches arbiter 238 implements a preference for accesses to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank (i.e., write to one bank is completed before writing to a different bank) (column 7, lines 1-8). In burst of write accesses 511, a write access labeled “W.sub.0” is a write access to rank 0 and a write access labeled “W.sub.1” is a write access to rank 1... Thus, in the example shown in first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (see column 10, lines 45-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67).
With respect to claim 5, Keil et al. does not teach wherein the first clock cycle and the second clock cycle are sequential clock cycle with no intervening clock cycles between the first clock cycle and the second clock cycle.
However, Shen et al. teaches wherein in a first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (i.e., write accesses between ranks are sequential) (see column 10, lines 52-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67)
With respect to claim 6, Keil et al. teaches wherein writing the first bit string to the first rank of the first memory bank includes writing the first bit string through a first rank pipeline (see column 4, lines 10-28; memory control circuit 101 is further configured to allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A… subsequent to the first write turn, the memory control circuit 101 is further configured to send write requests allocated to slots 103B to memory rank 102B) and wherein writing the second bit string to the second rank of the first memory bank includes writing the second bit string through the first rank pipeline (see column 4, lines 10-28; subsequent to the first write turn, the memory control circuit 101 is further configured to send write requests allocated to slots 103B to memory rank 102B).
With respect to claim 7, Keil et al. teaches wherein writing the first bit string to the first rank of the first memory bank includes writing the first bit string through a first rank pipeline (see column 4, lines 10-28; memory control circuit 101 is further configured to allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A… subsequent to the first write turn, the memory control circuit 101 is further configured to send write requests allocated to slots 103B to memory rank 102B) and wherein writing the second bit string to the second rank of the first memory bank includes writing the second bit string through the first rank pipeline (see column 4, lines 10-28; subsequent to the first write turn, the memory control circuit 101 is further configured to send write requests allocated to slots 103B to memory rank 102B).
With respect to claim 8, Keil et al. teaches a plurality of memory banks each comprising one or more respective memory ranks device (see column 4, lines 1-5; column 8, lines 27-35 and column 10, lines 11-16; memory control circuit 101 is configured to receive write requests 105 for memory ranks 102A and 102B. In various embodiments, write requests 105 includes a first subset of write requests to memory rank 102A, and a second subset of write requests to memory rank 102B);
a controller coupled to the plurality of memory banks (see Fig. 2 and column 6, lines 53-56; controller 210), wherein the controller is configured to:
write a first bit string, during a first clock cycle, to a first memory rank of a first memory bank among the plurality of memory banks (see column 10, lines 41-47; sending, by the memory control circuit, write requests allocated to the first set of slots to the first memory rank during the first write turn (block 704)); and
write a second bit string to a second memory rank of the first memory bank among the plurality of memory banks (see column 10, lines 48-55; in response to completing sending the write requests allocated to the first set of slots to the first memory rank, performing, by the memory control circuit, a rank switch (block 705). The method also includes sending, by the memory control circuit, write requests allocated to the second set of slots to the second memory rank in response to completing the rank switch), wherein:
Keil et al. does not explicitly teach write a second bit string, during a second clock cycle that is sequential to the first clock cycle, to a second memory rank; and the first bit string and the second bit string are written to the first rank and the second rank of the first memory bank among the plurality of memory banks prior to a third bit string being written to a second memory bank among the plurality of memory banks.
However, Shen et al. teaches However, Shen et al. teaches wherein in a first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (i.e., write accesses between ranks are sequential) (see column 10, lines 52-56); and arbiter 238 implements a preference for accesses to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank (i.e., write to one bank is completed before write to a different bank) (column 7, lines 1-8). In burst of write accesses 511, a write access labeled “W.sub.0” is a write access to rank 0 and a write access labeled “W.sub.1” is a write access to rank 1... Thus, in the example shown in first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (see column 10, lines 45-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67).
With respect to claim 9, Keil et al. teaches wherein the first memory rank of the first memory bank and the second memory rank of the first memory bank are associated with a first rank pipeline (see column 4, lines 10-28; memory control circuit 101 is further configured to allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A… subsequent to the first write turn, the memory control circuit 101 is further configured to send write requests allocated to slots 103B to memory rank 102B).
With respect to claim 10, Keil et al. teaches wherein the first memory rank of the first memory bank and the second memory rank of the first memory bank are associated with a same bank command arbiter (see column 4, lines 10-15 and column 5, lines 58-61; allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A... Arbitration circuit 305 is configured to allocate a particular write request to a corresponding slot).
With respect to claim 13, Keil et al. teaches a bank command arbiter to provide a plurality of bit strings to the controller to be written to the plurality of memory banks (see column 4, lines 10-15 and column 5, lines 58-61; allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A... Arbitration circuit 305 is configured to allocate a particular write request to a corresponding slot. Also in column 6, lines 4-23; Arbitration circuit 305 may, in various embodiments, be configured to select the initial memory rank according to one of various operating modes… arbitration circuit 305 may use a weight function to select the initial memory rank (i.e., an order of selecting ranks is determined)).
With respect to claim 14, Keil et al. teaches wherein the controller is further configured to assign the one or more respective memory ranks to the plurality of memory banks (see column 7, lines 63-67 and column 8, lines 25-35; memory rank 500 includes discrete memory devices 501A-501C. In various embodiments, memory rank 500 may correspond to any of memory ranks 102A or 102B… discrete memory devices 501A-501C may be implemented using discrete dynamic random-access memory (DRAM) circuits. In some embodiments, such DRAM circuits may include multiple banks that can include multiple pages).
With respect to claim 16, Keil et al. teaches a memory sub-system comprising a plurality of memory banks comprising a plurality of non-volatile memory devices (see column 7, lines 63-67 and column 8, lines 25-35; memory rank 500 includes discrete memory devices 501A-501C. In various embodiments, memory rank 500 may correspond to any of memory ranks 102A or 102B… discrete memory devices 501A-501C may be implemented using discrete dynamic random-access memory (DRAM) circuits. In some embodiments, such DRAM circuits may include multiple banks that can include multiple pages); and
a processing device coupled to the memory sub-system (see column 5, lines 10-13; memory access requests (e.g., write requests 105 and read requests 205) may be generated by a processor), wherein the processing device is configured to:
determine a first arbiter order for a first memory bank based on a first set of rank values of a first plurality of non-volatile memory devices within the first memory bank (see column 4, lines 10-15 and column 5, lines 58-61; allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A... Arbitration circuit 305 is configured to allocate a particular write request to a corresponding slot. Also in column 6, lines 4-23; Arbitration circuit 305 may, in various embodiments, be configured to select the initial memory rank according to one of various operating modes… arbitration circuit 305 may use a weight function to select the initial memory rank (i.e., an order of selecting ranks is determined));
provide a first set of corresponding bit strings to each of the first plurality of non-volatile memory devices within the first memory bank based on the first arbiter order (see column 4, lines 10-15; column 5, lines 58-61 and column 6, lines 4-23; allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A... Arbitration circuit 305 is configured to allocate a particular write request to a corresponding slot (i.e., writes are provided to rank slots selected));
determine a second arbiter order for a second memory bank based on a second set of rank values of a second plurality of non-volatile memory devices within the second memory bank (see column 4, lines 10-15 and column 5, lines 58-61; allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A... Arbitration circuit 305 is configured to allocate a particular write request to a corresponding slot. Also in column 6, lines 4-23; Arbitration circuit 305 may, in various embodiments, be configured to select the initial memory rank according to one of various operating modes… arbitration circuit 305 may use a weight function to select the initial memory rank (i.e., an order of selecting ranks is determined)); and
Keil et al. does not teach provide, subsequent to providing the first set of corresponding bit strings to each of the first plurality of non-volatile memory devices and in response to providing a corresponding bit string to a last non-volatile memory device from the first plurality of non-volatile memory devices, a second set of corresponding bit strings to each of the second plurality of non-volatile memory devices within the second memory bank based on the second arbiter order.
However, Shen et al. teaches wherein in a first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (i.e., write accesses between ranks are sequential) (see column 10, lines 52-56); and arbiter 238 implements a preference for accesses to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank (i.e., write to one bank is completed before write to a different bank) (column 7, lines 1-8) . In burst of write accesses 511, a write access labeled “W.sub.0” is a write access to rank 0 and a write access labeled “W.sub.1” is a write access to rank 1... Thus, in the example shown in first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (see column 10, lines 45-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67)
With respect to claim 18, Keil et al. does not teach wherein the first set of bit strings include a plurality of bit strings that are sequential bit strings provided to the first memory bank prior to providing intervening bit strings.
However, Shen et al. teaches a sequence of requests spread evenly over five ranks and divided equally between reads and writes can be picked from staging buffer 326 such that command queue 320 focuses on only two ranks at a time… pick requests from two preferred ranks until the requests from staging buffer are exhausted, and would then move to another rank (if a first rank is exhausted before the second rank) (see column 15, lines 23-34).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67).
Claim(s) 11-12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keil et al. (US 12,346,566) and Shen et al. (US 11,755,246) as applied to claims 8 and 16 above, and further in view of Tagawa (US 2007/0162715).
With respect to claim 11, Keil et al. teaches wherein the bit string is received at the controller and the second bit string is received at the controller (see column 10, lines 48-55; in
response to completing sending the write requests allocated to the first set of slots to the first memory rank, performing, by the memory control circuit, a rank switch (block 705). The method also includes sending, by the memory control circuit, write requests allocated to the second set of slots to the second memory rank in response to completing the rank switch).
Keil et al. does not teach wherein the first bit string is received at the controller from a first master command decoder and the second bit string is received at the controller from a second master command decoder, and wherein the bit string and second bit string is received at the controller prior to the controller receiving an intervening bit string.
However, Shen et al. teaches wherein arbiter 238 implements a preference for accesses to open pages to avoid the overhead of precharge and activation commands required to change memory pages, and hides overhead accesses to one bank by interleaving them with read and write accesses to another bank (i.e., write to one bank is completed before write to a different bank) (column 7, lines 1-8) . In burst of write accesses 511, a write access labeled “W.sub.0” is a write access to rank 0 and a write access labeled “W.sub.1” is a write access to rank 1... Thus, in the example shown in first timeline 510, the memory controller picks two write accesses to rank 0, followed by two write accesses to rank 1, followed by one write accesses to rank 0 (see column 10, lines 45-56)
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Keil et al. to include the above mentioned to efficiently schedule memory accesses (see Shen, column 6, lines 63-67).
Keil et al. and Shen et al. do not teach wherein the first bit string is received at the controller from a first master command decoder and the second bit string is received at the controller from a second master command decoder.
However, Tagawa teaches wherein based on an instruction that is output from the decoder buffer 23a, the command decoder 24a outputs the data that is buffered in the data buffer 22 to a memory rank 40a via a sub-memory bus 53a; or outputs the data that is buffered in the data buffer 22 to a memory rank 40b via a sub-memory bus 53b (see paragraph 46).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Keil et al. and Shen et al. to include the above mentioned to improve performance of the memory device (see Tagawa, paragraphs 15 and 16).
With respect to claim 12, Keil et al. teaches the first memory rank includes a first rank value and the second memory rank includes a second rank value, and wherein the first rank value and the second rank value each indicate an arbiter order in which the first bit string and the second bit string are written (see column 4, lines 10-15 and column 5, lines 58-61; allocate one or more of the first subset of write requests to corresponding slots of slots 103A, which are designated for memory rank 102A... Arbitration circuit 305 is configured to allocate a particular write request to a corresponding slot. Also in column 6, lines 4-23; Arbitration circuit 305 may, in various embodiments, be configured to select the initial memory rank according to one of various operating modes… arbitration circuit 305 may use a weight function to select the initial memory rank (i.e., an order of selecting ranks is determined)).
With respect to claim 17, Keil et al. and Shen et al. do not teach a plurality of master command decoders to generate the first set of corresponding bit strings and the second set of corresponding bit strings.
However, Tagawa teaches Based on an instruction that is output from the decoder buffer 23a, the command decoder 24a outputs the data that is buffered in the data buffer 22 to a memory rank 40a via a sub-memory bus 53a; or outputs the data that is buffered in the data buffer 22 to a memory rank 40b via a sub-memory bus 53b (see paragraph 46).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Keil et al. and Shen et al. to include the above mentioned to improve performance of the memory device (see Tagawa, paragraphs 15 and 16).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keil et al. (US 12,346,566) and Shen et al. (US 11,755,246) as applied to claim 8 and 14 above, and further in view of Goodwin et al. (US 6,226,709).
With respect to claim 15, Keil et al. does not explicitly teach wherein the one or more respective memory ranks are assigned to the plurality of memory banks such that each of the plurality of memory banks includes a unique memory rank value.
However, Goodwin et al. teaches wherein a memory bank is a group of SDRAM storage devices that shares common address and data path interconnect with other like groups of SDRAM storage devices… Finally, memory ranks are logical aggregations of pairs of memory banks (see column 4, lines 19-32); and each memory rank has a unique address or physical rank number (PRN) (see column 5, lines 4-5).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the apparatus taught by Keil et al. and Shen et al. to include the above mentioned to optimize the selection of operations (see Kim, paragraph 2).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keil et al. (US 12,346,566) and Shen et al. (US 11,755,246) as applied to claim 16 above, and further in view of Law (US 8,533,403)
With respect to claim 19, Keil et al. and Shen et al. do not teach a first bank controller to provide the first set of corresponding bit strings to the first plurality of non-volatile memory devices utilizing a first set of communication pipelines; and a second bank controller to provide the second set of corresponding bit strings to the second plurality of non-volatile memory devices utilizing a second set of communication pipelines.
However, Law teaches controllers 220, in one embodiment, are configured to receive requests from IC 10 and to provide corresponding commands to memory blocks 210 to cause performance of various memory operations. In the illustrated embodiment, each memory controller 220 is configured to send commands to a memory block 210 using a respective channel 216 (i.e., first and second bank controllers sending write requests to banks) (see column 7, lines 28-39).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Keil et al. and Shen et al. to include the above mentioned to permit efficient usage of the memory device (see Law, column 1, lines 40-42).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Keil et al. (US 12,346,566) and Shen et al. (US 11,755,246) as applied to claim 16 above, and further in view of Kim (US 2019/0180839).
With respect to claim 20, Keil et al. and Shen et al. do not teach a plurality of rank controllers to control functions for the first plurality of non-volatile memory devices with the first set of rank values and the second plurality of non-volatile memory devices with the second set of rank values.
However, Kim teaches wherein first rank 10 may include a first rank control circuit 100 that may receive or output the data DATA in response to the command CMD<1:N> in a normal mode (see paragraphs 24-25)… Each of the second to fourth ranks 20, 30 and 40 may be realized to have substantially the same configuration as the first rank 10 (see paragraph 28).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Keil et al. and Shen et al. to include the above mentioned to optimize the selection of operations (see Kim, paragraph 2).
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection, necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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