DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending, of which all pending claims are rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Agrawal et el. (US 6,366,508 B1) in view of Murai et al. (US 2002/0131307 A1), (Hereinafter Agrawal-Murai).
Regarding claim 1, Agrawal teaches, a memory (Agrawal: “FIG. 1 is a block diagram of an integrated circuit 10 having a memory array 12 and a built-in self repair (BISR) circuit 14” [Column 2, Lines 57 through 59, aka 2c57-59]), comprising:
a data array having a plurality of rows and columns, wherein a memory cell is located at an intersection of each row and column, wherein the data array is divided into a plurality of input/output (IO) groups and a redundant IO group, each group including a set of columns (Agrawal: ”FIG. 2 is a schematic diagram which illustrates the rows and columns within memory array 12 in greater detail. Memory array 12 includes a plurality of memory elements 200, which are arranged in a plurality of rows 202 and non-redundant columns 204. In one embodiment, memory array 12 has 128 physical rows 202 and 1024 physical columns 204. However, any number of rows and columns can be used in alternative embodiments. The memory elements 200 in each column 204 are coupled to a respective bitline 205. For simplicity, only one bitline 205 for each column 204 is shown in FIG. 2. However, multiple bitlines can be used for each column, such as a pair of complementary bitlines.’ [4c50-62]);
a column decoder configured to select one column from each IO group of the plurality of IO groups to provide selected data lines from the data array and one column from the redundant group to provide a redundant data line from the data array (Agrawal: “The column redundancy scheme of the present invention ensures that there is no timing penalty associated with the redundancy. Once the latches have been set to their appropriate states, the defective columns are replaced with redundant columns. No additional column address decoding is required to map column addresses from the defective column to the redundant column. Also, there are no additional elements inserted in the data path from each bitline to the respective data input-output node. The only penalty associated with the column redundancy scheme is the area consumed by the redundant columns and the support circuitry. However, the amount of the area penalty can be controlled by selecting the number of redundant columns per zone and the size of each zone. In addition, the column redundancy scheme of the present invention can be configured to repair as many defects as desired within a zone. Since it is generally found that defects occur in pairs, such defect pairs can be easily repaired with the column redundancy scheme of the present invention. The BISR logic required to implement the column redundancy scheme is not very complex, and the total cycle time during power-up that is required to load the latches is very small. Also, with this redundancy scheme, redundant columns can be shared between different IOs within a zone” [10c14-37]);
repair circuitry configured to, during normal operation, perform column repair using the selected one column from the redundant group to repair a defective column within one of the plurality of IO groups (Agrawal: “In one embodiment, BIST circuit 16 is adapted to test the memory elements within memory array 12 and identify any columns in memory array 12 in which a failure has occurred. BISR circuit 14 then attempts to repair the defect by replacing the defective column or columns with a redundant column or columns through the column multiplexer,...” [2c67-3c05] & [5c24-47);
Agrawal does not explicitly disclose, an output pin; read/write circuitry configured to, in response to a read access during a test mode in which built-in self-testing (BIST) is performed, output read data sensed from the redundant data line in parallel with read data sensed from all the selected data lines; and memory control circuitry configured to, in response to the read access during the test mode, provide the output read data sensed from the redundant data line external to the memory via the output pin.
However, Murai et al. teaches in an analogous art, [0103] In the case of detecting the existence of a defective bit, also in the data reading mode, both spare and memory cells can be accessed simultaneously, and test time in the data reading mode can be accordingly shortened. [0104] By combining the foregoing write data path and read data path, at the time of detecting the existence of a defective bit, test data can be simultaneously written in parallel into the normal and spare memory cells, and can be simultaneously read in parallel from the normal and spare memory cells, and whether the spare and normal memory cells can be simultaneously determined to be normal or defective. The test time can be therefore reduced greatly (see also: ‘input/output pin terminals’ [0100,0110-0111]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agrawal’s teachings of ‘memory having column redundancy’ with Murai’s teaching of ‘combining the write data path and read data path’ to provide a semiconductor memory device having a redundancy circuit for repairing a failure in normal memory cells by replacement. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. By doing so, test time for detecting a defective bit in the semiconductor memory device can be shortened.
Regarding claim 2, Agrawal-Murai teaches, the memory of claim 1, wherein the repair circuitry is further configured to, during the test mode, couple all the selected data lines to the read/write circuitry (Murai: “in the case of performing the determining operation by using the BIST circuit 110, by simultaneously accessing the normal memory cell and spare memory cell in the DRAM core, test time can be greatly shortened.” [0146]).
Regarding claim 3, Agrawal-Murai teaches, the memory of claim 2, wherein the repair circuitry is further configured to, for a read access during normal operation, select a set of N data lines from the selected data lines and the redundant data line to couple to the read/write circuitry, wherein N corresponds to a number of bits in an addressable data element of the data array for the read access (Murai: “In data reading mode, the data bits of the normal global data line pair to be replaced are replaced with read data bits output from the spare global data line pair, and the defective normal memory cell and normal memory cells related to the defective normal memory cell are replaced by the spare memory cells. Equivalently, the global data line pair is replaced by the spare global data line pair.” [0039]).
Regarding claim 4, Agrawal-Murai teaches, the memory of claim 3, wherein, for the read access during normal operation, an unselected data line outside the selected set of N data lines corresponds to a defective column repaired with the selected one column from the redundant IO group (Murai: “In data reading mode, the data bits of the normal global data line pair to be replaced are replaced with read data bits output from the spare global data line pair, and the defective normal memory cell and normal memory cells related to the defective normal memory cell are replaced by the spare memory cells. Equivalently, the global data line pair is replaced by the spare global data line pair.” [0039]).
Regarding claim 5, Agrawal-Murai teaches, the memory of claim 3, wherein the read data sensed from the redundant data line in parallel with read data sensed from the selected data lines includes N+1 data bits (Murai: “in the case of reading data, when a read command is supplied, after elapse of a predetermined time period (column latency), read data is output to the outside of the memory device via read data path 20. Since write data is supplied from a logic on the outside of the memory device, when read data lines 44 coupled to read data path 20 are coupled to the data input/output terminals in parallel with input data lines 40,”[0115]).
Regarding claim 6, Agrawal-Murai teaches, the memory of claim 1, wherein the memory control circuitry comprises: a plurality of flip flops configured as a scan chain, the scan chain having an output configured to serially output scan chain output data, wherein, during a scan mode of the memory, which is mutually exclusive with the test mode and with normal operation, the memory control circuitry is configured to provide the scan chain output data external to the memory via the output pin (Murai: ‘different mode of operations’ [0089]).
Regarding claim 7, Agrawal-Murai teaches, the memory of claim 6, wherein the memory control circuitry comprises: a multiplexer (MUX) having a first input configured to receive the scan chain output data, a second input configured to receive the output read data sensed from the redundant data line, and an output coupled to the output pin, wherein the MUX is configured to provide the scan chain output data to the output pin during the scan mode and provide the output read data sensed from the redundant data line to the output pin during the test mode (Murai: ‘multiplexer input outputs’ [0081, 0091, 0105]).
Regarding claim 8, Agrawal-Murai teaches, the memory of claim 7, wherein the MUX further comprises a control input coupled to receive a logical combination of a set of control signals used by the memory during at least one of the scan mode or normal operation with column repair (Murai: ‘different mode of operations’ [0089]).
Regarding claim 9, Agrawal-Murai teaches, the memory of claim 8, wherein the set of control signals includes a scan enable signal which selectively enables scan mode, a repair enable signal which selectively enables column repair, and one or more bits of a defective column indicator which indicates a defective column of the plurality of IO groups which is to be repaired when column repair is enabled (Murai: ‘different mode of operations’ [0089]).
Regarding claim 10, Agrawal-Murai teaches, the memory of claim 1, wherein the memory further comprises an input pin, and the memory control circuitry comprises: a plurality of flip flops configured as a scan chain, the scan chain having an input configured to serially receive scan chain input data, wherein, during a scan mode of the memory, which is mutually exclusive with the test mode and with normal operation, the memory control circuitry is configured to receive the scan chain input data via the input pin (Murai: ‘input/output pin terminals’ [0100,0110-0111]).
Regarding claim 11, Agrawal-Murai teaches, the memory of claim 10, wherein the memory control circuitry comprises: a one-to-two (1:2) decoder having an input coupled to the input pin to receive an input bit, a first output configured to provide the input bit to the read/write circuitry for a write access during normal operation, a second output configured to provide the input bit to the input of the scan chain during the scan mode, and a control input coupled to a receive a logical combination of a set of control signals (Murai: ‘decoder input/outputs’ [0127-0129]).
Regarding claim 12, Agrawal-Murai teaches, the memory of claim 11, wherein the set of control signals includes a scan enable signal which selectively enables scan mode, a repair enable signal which selectively enables column repair, and one or more bits of a defective column indicator which indicates a defective column of the plurality of IO groups which is to be repaired when column repair is enabled (Murai: ‘normal operation mode, test mode, and repair enable signals’ [0158]).
Regarding claim 13, Agrawal-Murai teaches, the memory of claim 11, wherein, in response to the write access during normal operation, the input bit is stored into the redundant IO in parallel with storing write data of the write access into the plurality of IO groups (Murai: “In the case of detecting the existence of a defective bit, also in the data reading mode, both spare and memory cells can be accessed simultaneously,” [0103]).
Regarding claim 14, Agrawal-Murai teaches, the memory of claim 1, wherein the repair circuitry comprises a plurality of multiplexers (MUXes), each coupled to receive a data line from a corresponding IO group of the plurality of IO groups, wherein each MUX of the plurality of MUXes is configured to, during normal operation, provide one of the data line from the corresponding IO group or an alternate data line to the read/write circuitry (Murai: ‘multiplexer data line’ [0101, 0093]).
Regarding claim 15, Agrawal-Murai teaches, the memory of claim 14, wherein the alternate data line of each MUX is one of a data line corresponding to a neighboring IO group or the redundant data line (Murai: ‘spare data lines’ [0023, 0025, 0032]).
Regarding claim 16, Agrawal teaches, a memory, comprising: …..; a data array having a plurality of rows and columns, wherein a memory cell is located at an intersection of each row and column, wherein the data array is divided into a plurality of input/output (IO) groups and a redundant IO group, each group including a set of columns (Agrawal: ”FIG. 2 is a schematic diagram which illustrates the rows and columns within memory array 12 in greater detail. Memory array 12 includes a plurality of memory elements 200, which are arranged in a plurality of rows 202 and non-redundant columns 204. In one embodiment, memory array 12 has 128 physical rows 202 and 1024 physical columns 204. However, any number of rows and columns can be used in alternative embodiments. The memory elements 200 in each column 204 are coupled to a respective bitline 205. For simplicity, only one bitline 205 for each column 204 is shown in FIG. 2. However, multiple bitlines can be used for each column, such as a pair of complementary bitlines.’ [Column 4, Lines 50 through 62, aka 4c50-62]);
a column decoder configured to select one column from each IO group of the plurality of IO groups to provide selected data lines and one column from the redundant group to provide a redundant data line (Agrawal: “The column redundancy scheme of the present invention ensures that there is no timing penalty associated with the redundancy. Once the latches have been set to their appropriate states, the defective columns are replaced with redundant columns. No additional column address decoding is required to map column addresses from the defective column to the redundant column. Also, there are no additional elements inserted in the data path from each bitline to the respective data input-output node. The only penalty associated with the column redundancy scheme is the area consumed by the redundant columns and the support circuitry. However, the amount of the area penalty can be controlled by selecting the number of redundant columns per zone and the size of each zone. In addition, the column redundancy scheme of the present invention can be configured to repair as many defects as desired within a zone. Since it is generally found that defects occur in pairs, such defect pairs can be easily repaired with the column redundancy scheme of the present invention. The BISR logic required to implement the column redundancy scheme is not very complex, and the total cycle time during power-up that is required to load the latches is very small. Also, with this redundancy scheme, redundant columns can be shared between different IOs within a zone” [10c14-37]);
Agrawal does not explicitly disclose, a plurality of flip flops configured as a scan chain having a scan input configured to serially receive scan chain input data and a scan output configured to serially output scan chain output data during a scan mode of the memory; a scan output pin configured to provide the scan chain output data from the scan output of the scan chain during the scan mode; read/write circuitry configured to, in response to a read access during a test mode in which built-in self-testing (BIST) is performed, output read data sensed from the redundant data line in parallel with read data sensed from all the selected data lines, wherein the scan mode and test mode are mutually exclusive; and memory control circuitry configured to, in response to the read access during the test mode, provide the output read data sensed from the redundant data line external to the memory via the scan output pin.
However, Murai et al. teaches in an analogous art, [0103] In the case of detecting the existence of a defective bit, also in the data reading mode, both spare and memory cells can be accessed simultaneously, and test time in the data reading mode can be accordingly shortened. [0104] By combining the foregoing write data path and read data path, at the time of detecting the existence of a defective bit, test data can be simultaneously written in parallel into the normal and spare memory cells, and can be simultaneously read in parallel from the normal and spare memory cells, and whether the spare and normal memory cells can be simultaneously determined to be normal or defective. The test time can be therefore reduced greatly (see also: ‘different mode of operations’ [0089]; ‘input/output pin terminals’ [0100,0110-0111]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Agrawal’s teachings of ‘memory having column redundancy’ with Murai’s teaching of ‘combining the write data path and read data path’ to provide a semiconductor memory device having a redundancy circuit for repairing a failure in normal memory cells by replacement. In a test mode, the data terminals are coupled in parallel to internal data line pairs and, simultaneously, a spare data line pair is coupled to the spare data terminal. By doing so, test time for detecting a defective bit in the semiconductor memory device can be shortened.
Regarding claim 17, Agrawal-Murai teaches, the memory of claim 16, further comprising repair circuitry configured to, during normal operation, perform column repair using the selected one column from the redundant group to repair a defective column within one of the plurality of IO groups, wherein the scan mode and test modes occur outside of normal operation, wherein the memory control circuitry comprises: a multiplexer (MUX) having a first input coupled to the scan output to receive the scan chain output data, a second input coupled to the read/write circuitry to receive the output read data sensed from the redundant data line, and an output coupled to the scan output pin (Murai: ‘multiplexer input outputs’ [0081, 0091, 0105]).
Regarding claim 18, Agrawal-Murai teaches, the memory of claim 17, further comprising a scan input pin, wherein the memory control circuitry comprises: a one-to-two (1:2) decoder having an input coupled to the scan input pin to receive an input bit, a first output configured to provide the input bit to the read/write circuitry for a write access during normal operation, and a second output configured to provide the input bit to the scan input of the scan chain during the scan mode (Murai: ‘decoder input/outputs’ [0127-0129]).
Regarding claim 19, Agrawal-Murai teaches, the memory of claim 18, wherein the MUX further comprises a control input coupled to receive a first logical combination of a set of control signals, and the one-to-two decoder further comprises a control input coupled to receive a second logical combination of the set of control signals (Murai: ‘decoder input/outputs’ [0127-0129]).
Regarding claim 20, Agrawal-Murai teaches, the memory of claim 19, wherein the set of control signals includes a scan enable signal which selectively enables scan mode, a repair enable signal which selectively enables column repair, and one or more bits of a defective column indicator which indicates a defective column of the plurality of IO groups which is to be repaired when column repair is enabled (Murai: ‘normal operation mode, test mode, and repair enable signals’ [0158])..
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Terai (US 2006/0053356 A1) teaches, an integrated circuit has a memory block including a RAM macro, a first scan circuit and a second scan circuit having a plurality of SFFs, and a parallel access memory BIST circuit. The first scan circuit has an input scan FF group capable of supplying data to the memory block and the second scan circuit has an output scan FF group capable of receiving data from the memory block. In a first test mode, a normal scan test is performed. In a second test mode, the parallel access memory BIST circuit outputs a BIST signal in parallel, and a selector selects and supplies the BIST signal to the input scan FF group, thereby testing the memory block.
When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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