Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 7 are slightly confusing. An amendment is recommended to claim 1 and 7. Claims 1 and 7 include a core board having not only a first principal surface and a second principal surface facing each other but also a through hole. The language is stylistically awkward and adds no real technical meaning. A clearer version would be: a core board having a first principal surface, a second principal surface facing the first principal surface, and a through hole.
Claim Rejections - 35 USC § 112
Claims 7-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "includes limitations to “the third electronic component.” There is no third electronic component introduced in claim 7. Therefore, this term lacks proper antecedent basis in the claim. Claims 8-13 are rejected as being dependent and including the same issue.
Claim(s) 1,3,4,7,9,10,12 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Christian (US 9204533).
Regarding claim 1, Christian teaches the following claim limitations.
A radio frequency module (Col. 1 line 20-25) comprising: a wiring board (multilayer substrate); a first electronic component and a second electronic component, the first electronic component and the second electronic component being built in the wiring board (the impedance matching circuit 100a); and a third electronic component disposed on the wiring board and connected to a matching circuit (RF Module mounted to surface (col 18 lines 6-7),
the wiring board including: a core board (20) having not only a first principal surface (top of 20) and a second principal surface (bottom 20) facing each other but also a through hole (20a) ; a first buildup layer (10,120…) stacked on the first principal surface of the core board; and a second buildup layer (30,40,50) stacked on the second principal surface of the core board, at least one of the first electronic component or the second electronic component being disposed at least partially inside the through hole of the core board (100a) , the third electronic component being disposed on the first buildup layer (Rf chip, col. 18 lines 6-7), the second electronic component being stacked on a surface of the first electronic component facing to the third electronic component in a thickness direction defined for the core board, and the second electronic component being a constituent component of the matching circuit.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2,5,8,14,15,17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Christian as applied to claim 1 above, and further in view of Toshiyuki (JP 2002290051).
Claim(s) 1-5,7-9,10,12,14-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Christian (US 9204533) in view of Toshiyuki (JP 2002290051).
Regarding claims 1 and 7, Christian teaches the following claim limitations.
A radio frequency module (Col. 1 line 20-25) comprising: a wiring board (multilayer substrate); a first electronic component and a second electronic component, the first electronic component and the second electronic component being built in the wiring board (the impedance matching circuit 100a); and a third electronic component disposed on the wiring board and connected to a matching circuit (RF Module mounted to surface (col 18 lines 6-7),
the wiring board including: a core board (20) having not only a first principal surface (top of 20) and a second principal surface (bottom 20) facing each other but also a through hole (20a) ; a first buildup layer (10,120…) stacked on the first principal surface of the core board; and a second buildup layer (30,40,50) stacked on the second principal surface of the core board, at least one of the first electronic component or the second electronic component being disposed at least partially inside the through hole of the core board (100a) , the third electronic component being disposed on the first buildup layer (Rf chip, col. 18 lines 6-7), and the second electronic component being a constituent component of the matching circuit (impedance matching circuit).
Christian doesn’t expressly teach the second electronic component being stacked on a surface of the first electronic component facing to the third electronic component in a thickness direction defined for the core board. In an analogous art, Toshiyuki teaches stacking elements inside the core of the wiring board can save space. See figure 4 elements 405 and 406.
Therefore it would have been obvious to have stacked the impedance matching elements of Christian within the hole of Christian in order to save real estate on the circuit board.
Regarding claims 2,8, the thickness of the core has limited possible characteristics. It could be very thin which has been the very old method of manufacturing a PCB such that all elements are mounted to the exterior. As is taught by Christian the circuit elements (impedance matching circuit) can be thicker than the thickness such that the combined elements extend beyond the core. See 100a compared to the thickness of core 20.
Regarding claim 3,4,5,9,10,12,14,15,16,17 and 18. Christian shows the impedance matching circuit to be within the hole as claimed. Note that the impedance matching circuit includes a capacitor and inductive elements. See figure 6. Toshiyuki shows the stacked features of these claims.
Claim(s) 6,13,19,20 are rejected under 35 U.S.C. 103 as being unpatentable over Christian and Toshiyuki as applied to claims 1,7,2 and 3 above, and further in view of Brunette (USP 7030712).
Regarding claim 6,13,19 and 20, Christian shows RF circuit elements or chips mounted on the surface of the of the multilayer substrate, but doesn’t expressly show that those elements are amplifiers. Brunette shows that RF circuits are typically including amplifiers as claimed. See figure 6.
Therefore it would have been obvious to have use an amplifier as one of the RF chips/circuits in Christian because amplifiers are commonly used in radio systems as shown by Brunette.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Christian and Toshiyuki as applied to claims 7 and 10 above, and further in view of Sugimoto (USP 7030712).
Sugimoto layer 5 and layer 15 show the building up layers as set forth in claim 11. Christian doesn’t expressly show the process of building up the layers to form the multilayer substrate. Therefore it would have been obvious to have build up the layers of Christian as show by Sugimoto in order to manufacture the above modified multilayer substrate.
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/BRIAN A ZIMMERMAN/Supervisory Patent Examiner, Art Unit 2686
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