DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuzmin et al., US patent No. 10,445,229 [hereinafter, Kuzmin].
As per claim 1:
Kuzmin teaches a method comprising: sending, by a controller, a command to perform an operation on a plurality of memory planes of a memory device [see figure 21, steps 2103-2107, for multi-plane read request; see figure 22; steps 2203-2207 for multi-plane write request] and performing the operation in response to the command on the plurality of memory planes in absence of sending additional commands [see figure 21, steps 2109-2111 for performing multi-plane data read without any additional command/request; see figure 22, steps 2209-2211, for multi-plane data write without and additional command/request].
As per claim 5:
Kuzmin also teaches the further claimed limitations of “wherein the plurality of memory planes are independent NAND memory planes coupled to corresponding electrical buses” [see figure 1, memory planes 108, which are NAND memory planes; see also col. 6, line 55].
As per claim 7:
Kuzmin also teaches the further claimed limitation of “the command is a sequential read command of the plurality of memory planes [see figure 31, step 2105; col. 58, lines 50-52; base address and address extension for accessing a second plane is disclosed].
As per claim 8:
Kuzmin also teaches that further claimed limitation of “the plurality of memory planes are sequential memory planes [see figure 1, memory planes 109; col. 6, lines 28-30; the memory planes are suitable for pipelined access] .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuzmin in view of Thacker et al., US 2013/0015578 [hereinafter, Thacker].
As per claim 6:
Kuzmin teaches a method as mentioned above.
Kuzmin, however, does not explicitly disclose that the corresponding electrical buses are coupled to an electrical pad.
Thacker explicitly teaches electrical pads 120 (see figure 1, para. 0041] for providing physical interface point on memory dies that allows the internal circuitry of the memory chips to connect to the outside world [as well-known in the art, Official Notice is hereby taken].
It would have been obvious to one having ordinary skill in the art, prior to the effective filing date of the claimed invention, to provide an electrical pad for each of the Kuzmin memory plane. This is because it is necessary element for the internal circuitry of the memory chips to connect to the outside world.
Allowable Subject Matter
Claims 9-20 are allowed over the prior art od record. The claimed invention is directed to accessing multiple memory planes using a single command/request. By doing so the system sends dummy clock signals from the controller to the memory and the memory returns dummy data during the period of time when the memory device is switching between performing the operation from the first memory plane to the second memory plane. By doing so the quantity of commands can relatively be reduced. Thus, the quantity of time typically utilized to generate a plurality of commands employed by previous approaches can also be reduced to a quantity of time utilized to generate a single command [see the specification , paragraph 0016]. None of the prior art of record teaches the claimed features related to the claimed dummy clock signals and dummy data of the independent claims 9 and 17.
The closest prior art reference is Kuzmin et al., US patent No. 10,445,229. Kuzmin teach single command to access multiple memory planes. But Kuzmin is silent about the use dummy clock signals and dummy data as claimed.
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The claims are also allowed over the prior art of record for the same reasons as set forth for claims 9-20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lu et al., US 2023/0280929, simplifying the number of issued command sequences to use single command sequence to achieve the purpose of multiple command sequences for the communication between flash memory device and its controller [see para. 0053].
Lee, US 2016/0011779, teaches multi-plane read sequence [see para. 0185].
Matsuyama et al., US 2012/0166711, teaches single write command for writing data into multiple memory planes [see para. 0047]
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/HIEP T NGUYEN/ Primary Examiner, Art Unit 2137
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