Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A (claims 1-10) in the reply filed on 8/10/26 is acknowledged. The traversal is on the ground(s) that the requirement does not set forth the reasons and analysis required to support it and does not establish a serious search burden or examination burden. This is not found persuasive.
First, it should be noted that the reasons were clearly set forth. The requirement stated “The species are independent or distinct because the conductive layer can either be above or below the electrode layer, but not both; and the cover electrode can either be longer or shorter than the conductive resin layer, but not both. In addition, these species are not obvious variants of each other based on the current record.” Clearly these Species are independent and distinct, based on the mutually exclusive positioning of the conductive resin layer and the length of the cover electrode. There are no embodiments showing the conductive resin layer can be both on the electrode layers in the band portion and under the electrode layers in the band portion; therefore, the locations of the conductive resin layer are mutually exclusive. Further, there are no embodiments showing the cover electrodes are both longer than the conductive resin layer and shorter than the conductive resin layer; therefore, the lengths of the cover electrodes are mutually exclusive.
Further, as noted in the requirement, the mutually exclusive features each require different search terms (i.e. materially different search strategies) to determine the claimed placement location of the conductive resin layer and/or the related length of the cover electrodes.
With respect to Species B and C, claims 11-13 and 16-20 are generic to both Species, but claims 11-13 and 16-20 are not generic to Species A.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 2017/0154729).
Regarding claim 1, Lee discloses a multilayer electronic component (figs. 5 and 6 and note similar components in figs. 1-3, paragraph [0075]) comprising: a body (figs. 5 and 6 (210), see also fig. 1 (110)) including a dielectric layer (figs. 5 and 6 (211), see also fig. 2 (111)) and first and second internal electrodes (figs. 5 and 6 (221) and (222), see also fig. 2 (121) and (122)) alternately disposed with the dielectric layer in a first direction (figs. 5 and 6 (T)), the body including a first surface and a second surface opposing each other in the first direction (figs. 5 and 6), a third surface and a fourth surface, connected to the first and second surfaces and opposing each other in a second direction (figs. 5 and 6 (L)), and a fifth surface and a sixth surface, connected to the first to fourth surfaces and opposing each other in a third direction (fig. 1 (W)); a first external electrode (figs. 5 and 6 (31), (33), (35)) including a first connection portion disposed on the third surface (figs. 5 and 6), and a first band portion extending from the first connection portion onto a portion of the first surface and a portion of the second surface (figs. 5 and 6); and a second external electrode (figs. 5 and 6 (32), (34), (36)) including a second connection portion disposed on the fourth surface, (figs. 5 and 6) and a second band portion extending from the second connection portion onto a portion of the first surface and a portion of the second surface (figs. 5 and 6), wherein the first external electrode includes a first electrode layer (figs. 5 and 6 (31)) connected to the first internal electrode (figs. 5 and 6 (221)), and a first conductive resin layer (figs. 5 and 6 (33)) disposed on the first electrode layer in the first band portion (figs. 5 and 6), the first conductive resin layer including a second conductive metal and a thermosetting resin (paragraphs [0050]-[0052]), the second external electrode includes a second electrode layer (figs. 5 and 6 (32)) connected to the second internal electrode (figs. 5 and 6 (222)), and a second conductive resin layer (figs. 5 and 6 (34)) disposed on the second electrode layer in the second band portion (figs. 5 and 6), the second conductive resin layer including the second conductive metal and the thermosetting resin (paragraphs [0050]-[0052]), the first electrode layer and the second electrode layer include a first conductive metal and glass (paragraphs [0047]-[0049]), the first conductive resin layer is not disposed on the first connection portion (figs. 5 and 6), and the second conductive resin layer is not disposed on the second connection portion (figs. 5 and 6).
Regarding claim 2, Lee discloses the multilayer electronic component of claim 1, wherein the first electrode layer is in contact with the first internal electrode (figs. 5 and 6), and the second electrode layer is in contact with the second internal electrode (figs. 5 and 6).
Regarding claim 3, Lee discloses the multilayer electronic component of claim 1, wherein, a portion connecting the first connection portion and the first band portion is a first edge portion (fig. 6, corner portion where 33 overlaps 31), and a portion connecting the second connection portion and the second band portion is a second edge portion (fig. 6, corner portion where 34 overlaps 32), the first conductive resin layer covers at least a portion of the first electrode layer in the first edge portion (fig. 6), and the second conductive resin layer covers at least a portion of the second electrode layer at the second edge portion (fig. 6).
Regarding claim 4, Lee discloses the multilayer electronic component of claim 1, wherein the first conductive resin layer (fig. 5 (33)) is disposed to not extend beyond an extension line of the first surface and an extension line of the second surface (fig. 5), and the second conductive resin layer (fig. 5 (34)) is disposed to not extend beyond the extension line of the first surface and the extension line of the second surface (fig. 5).
Regarding claim 5, Lee discloses the multilayer electronic component of claim 1, wherein the first external electrode further comprises a first plating layer (fig. 5 (35)) disposed on the first conductive resin layer (fig. 5), the first plating layer including Ni (paragraphs [0055]-[0056]), and the second external electrode further comprises a second plating layer (fig. 5 (36)) disposed on the second conductive resin layer (fig. 5), the second plating layer including Ni (paragraphs [0055]-[0056]).
Regarding claim 6, Lee discloses the multilayer electronic component of claim 5, wherein the first plating layer (fig. 5 (35)) covers the first electrode layer and the first conductive resin layer (fig. 5), and the second plating layer (fig. 5 (36)) covers the second electrode layer and the second conductive resin layer (fig. 5).
Regarding claim 8, Lee discloses the multilayer electronic component of claim 2, wherein the first electrode layer directly contacts the first internal electrode (figs. 5 and 6).
Regarding claim 9, Lee discloses the multilayer electronic component of claim 1, wherein an end of the first conductive resin layer is disposed on a corner of the first electrode layer (fig. 6).
Regarding claim 10, Lee discloses the multilayer electronic component of claim 1, wherein the first electrode layer is a sintered electrode (paragraph [0085]).
Claim(s) 1-3 and 5-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang et al. (US 2023/0290572).
Regarding claim 1, Kang discloses a multilayer electronic component (fig. 8) comprising: a body (fig. 8 (110)) including a dielectric layer (fig. 8 (111)) and first and second internal electrodes (fig. 8 (121) and (122)) alternately disposed with the dielectric layer in a first direction (fig. 8 (Z)), the body including a first surface and a second surface opposing each other in the first direction (fig. 8), a third surface and a fourth surface, connected to the first and second surfaces and opposing each other in a second direction (fig. 8 (X)), and a fifth surface and a sixth surface, connected to the first to fourth surfaces and opposing each other in a third direction (fig. 8 (Y)); a first external electrode (fig. 8 (131’)) including a first connection portion disposed on the third surface (fig. 8 (A1)), and a first band portion extending from the first connection portion onto a portion of the first surface and a portion of the second surface (fig. 8 (B1)); and a second external electrode (fig. 8 (132’)) including a second connection portion disposed on the fourth surface, (fig. 8 (A2)) and a second band portion extending from the second connection portion onto a portion of the first surface and a portion of the second surface (fig. 8 (B2)), wherein the first external electrode includes a first electrode layer (fig. 8 (131a’)) connected to the first internal electrode (fig. 8 (121)), and a first conductive resin layer (fig. 8 (131b’)) disposed on the first electrode layer in the first band portion (fig. 8), the first conductive resin layer including a second conductive metal and a thermosetting resin (paragraph [0071], note: epoxy resin is a thermosetting resin), the second external electrode includes a second electrode layer (fig. 8 (132a’)) connected to the second internal electrode (fig. 8 (122)), and a second conductive resin layer (fig. 8 (132b’)) disposed on the second electrode layer in the second band portion (fig. 8), the second conductive resin layer including the second conductive metal and the thermosetting resin (paragraph [0071] note: epoxy resin is a thermosetting resin), the first electrode layer and the second electrode layer include a first conductive metal and glass (paragraphs [0068] and [0120]), the first conductive resin layer is not disposed on the first connection portion (fig. 8), and the second conductive resin layer is not disposed on the second connection portion (fig. 8).
Regarding claim 2, Kang discloses the multilayer electronic component of claim 1, wherein the first electrode layer is in contact with the first internal electrode (fig. 8), and the second electrode layer is in contact with the second internal electrode (fig. 8).
Regarding claim 3, Kang discloses the multilayer electronic component of claim 1, wherein, a portion connecting the first connection portion and the first band portion is a first edge portion (fig. 8, corner portion between A1 and B1), and a portion connecting the second connection portion and the second band portion is a second edge portion (fig. 8, corner portion between A2 and B2), the first conductive resin layer covers at least a portion of the first electrode layer in the first edge portion (fig. 8), and the second conductive resin layer covers at least a portion of the second electrode layer at the second edge portion (fig. 8).
Regarding claim 5, Kang discloses the multilayer electronic component of claim 1, wherein the first external electrode further comprises a first plating layer (fig. 8 (131c’)) disposed on the first conductive resin layer (fig. 8), the first plating layer including Ni (paragraph [0115]), and the second external electrode further comprises a second plating layer (fig. 8 (132c’)) disposed on the second conductive resin layer (fig. 8), the second plating layer including Ni (paragraph [0115]).
Regarding claim 6, Kang discloses the multilayer electronic component of claim 5, wherein the first plating layer (fig. 8 (131c’)) covers the first electrode layer and the first conductive resin layer (fig. 8), and the second plating layer (fig. 8 (132c’)) covers the second electrode layer and the second conductive resin layer (fig. 8).
Regarding claim 7, Kang discloses the multilayer electronic component of claim 5, wherein the first external electrode further comprises a third plating layer disposed on the first plating layer (paragraph [0115]), the third plating layer including Sn (paragraph [0115]), and the second external electrode further comprises a fourth plating layer disposed on the second plating layer (paragraph [0115]), the fourth plating layer including Sn (paragraph [0115]).
Regarding claim 8, Kang discloses the multilayer electronic component of claim 2, wherein the first electrode layer directly contacts the first internal electrode (fig. 8).
Regarding claim 9, Kang discloses the multilayer electronic component of claim 1, wherein an end of the first conductive resin layer is disposed on a corner of the first electrode layer (fig. 8).
Regarding claim 10, Kang discloses the multilayer electronic component of claim 1, wherein the first electrode layer is a sintered electrode (paragraph [0068]).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2021/0065984.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Timothy J Dole whose telephone number is (571)272-2229. The examiner can normally be reached M-F 6:30am-2:30pm.
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/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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