Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, the claim 9 recites the claim limitation “generate a plurality of command signals to be provided to a memory device…” However, the claim 9 recites the claim limitation “a first flip-flop circuit to receive command data from a command data processing circuit of a memory device…a clock processing circuit of the memory device.” It is unclear whether the claim limitation “be provided to a memory device” refers to “the memory device.” For the purpose of the examination, examiner interprets the limitation as “to be provided to the memory device.”
The claim 9 recites the claim limitation “generate a plurality of command signals to be provided to a memory device to generate command data in response to the plurality of command signals.” However, the claim 9 also recites the limitation “a first flip-flop circuit to receive command data from a command data processing circuit of a memory device.” It is unclear whether the claim limitations “to generate command data in response to…” refers to “to receive command data from…” For the purpose of the examination, examiner interprets the limitation “generate a plurality of command signals to be provided to a memory device to generate command data in response to the plurality of command signals” as “generate a plurality of command signals to be provided to a memory device to generate the command data in response to the plurality of command signals.”
The claim 9 further recites the limitation “generate a first plurality of clock signals that correspond to the plurality of command signals to be provided to the memory device.” However, the claim 9 recites the limitation “a second flip-flop circuit to receive clock signals from a clock processing circuit of the memory device.” It is unclear whether the claim limitation “a first plurality of clock signals” refers to “clock signals from a clock processing circuit of the memory device.”
The claim 9 further recites the limitation “wherein the memory device is to generate clock signals in response to the first plurality of clock signals and the second plurality of clock signals to be provided to the second flip-flop circuit.” However, as discussed above, the claim 9 recites the limitation “a second flip-flop circuit to receive clock signals from a clock processing circuit of the memory device.” It is unclear whether “the memory device is to generate clock signals in response to…” refers to “a second flip-flop circuit to receive clock signals from a clock processing circuit of the memory device.” For the purpose of the examination, examiner interprets the limitations of the “the memory device is to generate clock signals in response to…” as “the memory device is to generate the clock signals in response to…”
Regarding claims 10-16, the claims 10-16 inherit the deficiency of the independent claim 9. Therefore, the claims 10-16 are rejected under 35 U.S.C. §112(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Agrawal et al. (United States Patent US 8713221), hereinafter Agrawal.
Regarding claim 1, Agrawal teaches a method comprising: providing, by a controller, a plurality of control signals and a first plurality of clock signals to a memory device, wherein the first plurality of clock signals is greater than the plurality of control signals ([Col. 2 Lines 63-65] “The write pulse may enable the producer clock domain to write to the FIFO queues.” [Col. 3 Lines 33-38] “the write frequency of producer clock domain 110 may be different (e.g., higher) than the read frequency of consumer clock domains 130 and each of con-sumer clock domains 130 may be independent of one another but operate at the same clock frequency (i.e., the consumer clocks are plesio-synchronous clocks).” [Col. 3 Line s53-60] “producer clock domain 110 may communicate with a number of consumer clock domains, illustrated as read component 230-1 through read component 230-N (collectively referred to herein as "read components 230," and singularly as "read component 230"), which may correspond to consumer clock domains 130-1 through 130-N, respectively.” Signals to read and write is interpreted as a plurality of control signals. Clock signal in producer clock domain and a plurality of clock signals in a plurality of consumer domains are interpreted as a first plurality of clock signals. Furthermore, as each of the consumer domains receives rClk1…rClkN while a producer clock domain receives at wClk, the plurality of clock signals are greater than the signals for read and write operations.);
receiving, at the controller, a first plurality of data signals corresponding to the plurality of control signals and a second plurality of clock signals corresponding to a first portion of the first plurality of clock signals from the memory device; and receiving, at the controller, a second plurality of data signals and a third plurality of clock signals corresponding to a second portion of the first plurality of clock signals from the memory device ([Col. 4 Lines 8-11] “Read components 230 may correspondingly read, at each respective read clock cycle rClkl through rClkN, R bits from an asynchronous FIFO queue 120, where R and W may be different.” The data is written to asynchronous FIFOs based on the signal to control read and write operations. The signals to control read and write operations for each of the consumer domains are controlled based on the read clock signal of its corresponding consumer domain. Furthermore, each of the read clock signal is divided using a clock driver that “may receive a read clock from one of read components 230 and operate to divide the frequency of the read clock to a lower frequency” as in Col. 4 Lines 28-30.).
Regarding claim 2, Agrawal teaches determining, at the memory device, a quantity of control signals received from the controller ([Col. 6 Lines 17-36] “Process 500 may further include, when a read operation is detected (block 510-YES), incrementing a credit counter, in proportion to the size of the read operation, corresponding to the detected read operation (block 520)…When any of the counters is greater than the threshold (block 530-YES), the threshold may be subtracted from every one of the counters (block 540). Additionally, a write pulse may be issued to the producer clock domain (block 550), indicating that a write operation to asynchronous FIFOs 120 may be performed.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Agrawal in view of Yu et al. (United States Patent Application Publication US 2016/0239220), hereinafter Yu.
Regarding claim 5, Agrawal teaches all the limitations of the method of claim 1, as discussed above.
However, Agrawal does not teach wherein the second plurality of data signals comprise garbage data.
Yu teaches wherein the second plurality of data signals comprise garbage data ([0040] “Before transmitting a valid DQS signal, the flash memory 110 transmits a dummy DQS signal to cope with a case where a duty rate of the DQS signal does not match. The memory controller 120 disregards dummy data DMl and DMZ by the dummy DQS signal and sequentially stores only valid data Dl to D4 by the valid DQS signal in the first latch circuit LATl of the FIFO circuit 122 (see FIG. 1).” Garbage data is interpreted as data that is inaccurate, corrupted, useless or servers no valid purpose. Dummy DQS is not to execute operation, which is interpreted as garbage data.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Agrawal by incorporating the teaching of Yu of garbage data. They are all directed toward FIFOs. As recognized by Yu, “data is transmitted between the flash memory and the memory controller at high speed. The storage device uses a data strobe signal DQS to stably transmit the data. However, a pulse width of the data strobe signal DQS may be reduced by resistance of a signal line or the like. If the pulse width of the data strobe signal DQS becomes narrow, data may not be stably transmitted” ([0005]). By adding dummy data signals or garbage data, the garbage data copes with a case where a duty rate of the DQS signal does not match ([0040]). Therefore, it would be advantageous to incorporate the teaching of Yu of garbage data.
Allowable Subject Matter
Claims 3, 4, 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Agrawal teaches a system with a producer clock domain and one or more consumer clock domains that exchange data using FIFO queues. Agrwal further teaches frequency of the producer clock domain and frequency of the consumer clock domains may be different and each of consumer clock domains may be independent of one another. However, Agrawal does not teach “generating, at the controller, the first portion of the first plurality of clock signals based on a quantity of the plurality of control signals and the second portion of the first plurality of clock signals based on a pathway between the controller and the memory device,” “wherein the first plurality of data signals corresponding to the plurality of control signals correspond to values stored by the memory device,” “wherein the second plurality of data signals corresponding to the second portion of the first plurality of clock signals do not correspond to values stored by the memory device,” “generating, by the controller, a quantity of the second portion of the first plurality of clock signals based on a first-in first-out (FIFO) device positioned between the controller and the memory device.”
Yu teaches a flash memory to transmit a dummy data strobe signal DQS before transmitting a valid DQS signal to cope with a case where a duty rate of the DQS signal does not match. However, Yu does not teach “generating, at the controller, the first portion of the first plurality of clock signals based on a quantity of the plurality of control signals and the second portion of the first plurality of clock signals based on a pathway between the controller and the memory device,” “wherein the first plurality of data signals corresponding to the plurality of control signals correspond to values stored by the memory device,” “wherein the second plurality of data signals corresponding to the second portion of the first plurality of clock signals do not correspond to values stored by the memory device,” “generating, by the controller, a quantity of the second portion of the first plurality of clock signals based on a first-in first-out (FIFO) device positioned between the controller and the memory device.”
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Agrawal teaches a system with a producer clock domain and one or more consumer clock domains that exchange data using FIFO queues. Agrwal further teaches frequency of the producer clock domain and frequency of the consumer clock domains may be different and each of consumer clock domains may be independent of one another. However, Agrawal does not teach “identify a first set of output values based on the received second plurality of command signals and the third plurality of clock signals within the FIFO device; and ignore a second set of output values based on the third plurality of command signals and the fourth plurality of clock signals.”
Yu teaches a flash memory to transmit a dummy data strobe signal DQS before transmitting a valid DQS signal to cope with a case where a duty rate of the DQS signal does not match. However, Yu does not teach “identify a first set of output values based on the received second plurality of command signals and the third plurality of clock signals within the FIFO device; and ignore a second set of output values based on the third plurality of command signals and the fourth plurality of clock signals.”
Korger (United States Patent US 6880050) teaches a system indicating active tag bits within valid entries of a dual-clock FIFO data buffer used to transfer data between two clock domains. However, Korger does not teach “identify a first set of output values based on the received second plurality of command signals and the third plurality of clock signals within the FIFO device; and ignore a second set of output values based on the third plurality of command signals and the fourth plurality of clock signals.”
Lim et al. (United States Patent US 11373694) teaches a generic physical layer providing unified architecture for interfacing with an external memory device using a transmit data path for transmitting a parallel data to external memory device and a reeving data path for receiving a serial data from the external memory data path using a FIFO circuit, a data rotator, and an adjustable-delay logic for delay tuning and a per-bit-deskew for multi-lane support. However, Lim does not teach “identify a first set of output values based on the received second plurality of command signals and the third plurality of clock signals within the FIFO device; and ignore a second set of output values based on the third plurality of command signals and the fourth plurality of clock signals.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hoang (United States Patent US 6067585) teaches an adaptive interface controller that can operate with segments of different protocol and transmission rates in a single integrated device.
Jin et al. (United States Patent US 5920897) teaches apparatus and method for providing multiple channel clock-data alignment according to a single clock through a use of a FIFO.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HYUN SOO KIM whose telephone number is (571)270-1768. The examiner can normally be reached Monday - Friday 8:30 am - 5:30 pm.
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/HYUN SOO KIM/Examiner, Art Unit 2176
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