Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 8-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaneda (US 20150102510 A1) in view of Bish (US 6906413 B2).
Regarding claim 1, Kaneda teaches an electronic component mounting substrate (Fig 3; 60), comprising:
an electronic component (Fig 3; semiconductor chip 70);
a printed wiring board (Fig 3; 10) configured to mount the electronic component thereon ([0045]; wherein the wiring board is manufactured to be mounted with electronic components, such as a semiconductor chip);
and the printed wiring board includes an upper build-up part (Fig 1A; layers 50-56) and a lower build-up part (Fig 1A; layers 31-36) such that the upper build-up part is configured to mount the electronic component thereon ([0094]; pads P1 in layer 56 are configured to mount the electronic component) and includes an uppermost resin insulating layer not containing a reinforcing material (Fig 1A; [0078]; layers 51, 53, and 55 are able to be made of only resin) and that the lower build-up part includes a lowermost resin insulating layer comprising a reinforcing material (Fig 1A; [0058]; layers 31, 33, and 35 may contain a filler in the resin).
Kaneda does not teach a cover configured to accommodate and seal the electronic component mounted on the printed wiring board, wherein the cover has an upper portion and a support portion supporting the upper portion such that the upper portion has a thickness of 2 mm or more.
However, Bish teaches in figure 1 a cover (16) configured to accommodate and seal the electronic component (12) mounted on the printed wiring board (10), wherein the cover has an upper portion (upper part of 16) and a support portion (sides 9) supporting the upper portion such that the upper portion has a thickness of 2 mm or more (Col. 5 lines 25-27; wherein the thickness of 16 is preferably between 0.5 mm to 8 mm).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electronic component mounting substrate of Kaneda to include a cover for the electronic component, in order to protect the electronic components (Bish Col. 4, lines 44-46).
Regarding claim 2, Kaneda teaches in figure 3 an electronic component mounting substrate (60).
Kaneda does not teach wherein a cover is formed such that the thickness of the upper portion is in a range of 3 mm to 10 mm.
However, Bish teaches in figure 1 wherein a cover (16) is formed such that the thickness of the upper portion is in a range of 3 mm to 10 mm (Col. 5 lines 25-27; wherein the thickness of 16 is preferably between 0.5 mm to 8 mm).
“Where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, Bish discloses that the cover has a thickness of an upper portion in a range of 0.5 mm to 8 mm, which overlaps the claimed range of 3 mm to 10 mm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the claimed cover thickness 3 mm to 10 mm, as taught by Bish, in order to provide sufficient mechanical protection for electronic components of various sizes mounted to the printed wiring board (Bish Col. 4, lines 44-46).
Regarding claim 3, Kaneda teaches in figure 3 an electronic component mounting substrate (60).
Kaneda does not teach wherein a cover is formed such that the thickness of the upper portion is in a range of 3 mm to 5 mm.
However, Bish teaches in figure 1 wherein a cover (16) is formed such that the thickness of the upper portion is in a range of 3 mm to 5 mm (Col. 5 lines 25-27; wherein the thickness of 16 is preferably between 0.5 mm to 8 mm).
“Where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, Bish discloses that the cover has a thickness of an upper portion in a range of 0.5 mm to 8 mm, which overlaps the claimed range of 3 mm to 5 mm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the claimed cover thickness 3 mm to 5 mm, as taught by Bish, in order to provide sufficient mechanical protection for electronic components of various sizes mounted to the printed wiring board (Bish Col. 4, lines 44-46).
Regarding claim 4, Kaneda teaches an electronic component mounting substrate (Fig 3; 60), wherein the upper build-up part (Fig 1A; layers 50-56) includes a plurality of conductor layers (Fig 1A; layers 50, 52, 54, 56) and a plurality of resin insulating layers (Fig 1A; layers 51, 53, 55) including the uppermost resin insulating layer and each not containing a reinforcing material (Fig 1A; [0078]; layers 51, 53, and 55 are able to be made of only resin), and the lower build-up part (Fig 1A; layers 31-36) includes a plurality of conductor layers (Fig 1A; layers 32, 34, 36) and a plurality of resin insulating layers (layers 31, 33, 35) including the lowermost resin insulating layer and each comprising a reinforcing material (Fig 1A; [0058]; layers 31, 33, and 35 may contain a filler in the resin).
Regarding claim 8, Kaneda teaches an electronic component mounting substrate (Fig 3; 60), wherein the upper (Fig 1A; 50-56) and lower build-up parts (Fig 1A; 31-36) are formed such that the lowermost resin insulating layer has a thickness that is greater than a thickness of the uppermost resin insulating layer ([0079]; wherein the insulating layers 51, 53, and 55 are thinner than the insulating layers in structure 11, such as 31, 33, and 35).
Regarding claim 9, Kaneda teaches an electronic component mounting substrate (Fig 3; 60) and a printed wiring board (Fig 3; 10) with a total thickness amounting to a range of 0.437 mm to 1.525 mm. The following thickness ranges of each layer, when added, yield this total thickness range of the board: [0054] wherein layer 20 is 200-1000 μm; [0058] wherein layers 31, 33, and 35 are 20-45 μm and layers 32 and 34 are 15-35 μm; [0067] wherein layers 41, 43, and 45 are each 20-45 μm and layers 42, 44, and 46 are each 15-35 μm; [0099] wherein the thickness of section 12, T1, is 12-30 μm; and [0099] wherein the thickness of section 13, T2, is 30-50 μm.
Kaneda does not teach a cover with a thickness of an upper portion, wherein the cover is formed such that the thickness of the upper portion is in a range of 5 to 7 times a thickness of the printed wiring board.
However, 5 to 7 times the thickness range of the printed wiring board of Kaneda amounts to 2.185 mm to 10.675 mm, and Bish teaches in figure 1 a cover (16) with a thickness of an upper portion (Col. 5 lines 25-27; wherein the thickness of 16 is preferably between 0.5 mm to 8 mm).
“Where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, Kaneda as modified by Bish discloses that the printed wiring board has a thickness in a range of 0.437 mm to 1.525 mm and the cover has a thickness of an upper portion in a range of 0.5 mm to 8 mm, which overlaps the claimed range of the cover thickness being 5 to 7 times the printed wiring board thickness. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the claimed cover thickness being 5 to 7 times the printed wiring board thickness, as taught by a modified Kaneda, in order to provide sufficient mechanical protection for electronic components of various sizes mounted to the printed wiring board.
Regarding claim 10, Kaneda teaches an electronic component mounting substrate (Fig 3; 60), wherein a printed wiring board (Fig 3; 10) has a thickness (wherein the total thickness of the wiring board 10 is in a range of 0.437 mm to 1.525 mm). The following thickness ranges of each layer in Kaneda, when added, yield this total thickness range of the board: [0054] wherein layer 20 is 200-1000 μm; [0058] wherein layers 31, 33, and 35 are 20-45 μm and layers 32 and 34 are 15-35 μm; [0067] wherein layers 41, 43, and 45 are each 20-45 μm and layers 42, 44, and 46 are each 15-35 μm; [0099] wherein the thickness of section 12, T1, is 12-30 μm; and [0099] wherein the thickness of section 13, T2, is 30-50 μm.
Kaneda does not explicitly teach that the printed wiring board has a thickness in a range of 0.5 mm to 0.7 mm.
However, “Where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). In the instant case, Kaneda discloses that the printed wiring board has a thickness in a range of 0.437 mm to 1.525 mm, which overlaps the claimed range of 0.5 mm to 0.7 mm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the claimed thickness range of 0.5 mm to 0.7 mm, as taught by Kaneda, in order to allow the wiring board to be accommodated into multiple electrical systems while still preventing warping of the board.
Regarding claim 11, Kaneda teaches an electronic component mounting substrate (Fig 3; 60), wherein the printed wiring board (Fig. 3; 10) is formed with a length of a short side of the printed wiring board and a length of a long side of the printed wiring board ([0052]; wherein the board can have any plan-view shape and size).
Kaneda does not explicitly teach that a length of a short side of the printed wiring board is 70 mm or more and a length of a long side of the printed wiring board is 250 mm or less.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to use a short side of 70 mm or more and a long side of 250 mm or less, in order to provide a sufficient area to mount enough electronic components to the wiring board to perform circuit operations.
Regarding claim 12, Kaneda teaches in figure 3 an electronic component mounting substrate (60).
Kaneda does not teach a cover with a material.
However, Bish teaches in figure 1 a cover (16) with a material (Col. 3, lines 57-62; wherein the lid can be several materials, including a metal like copper).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate of Kaneda to include a cover with a material chosen in order to provide high thermal conductivity (Bish Col. 3, lines 57-62).
Bish fails to explicitly teach “a material having a Young's modulus of 100 GPa or more at 25° C”. However, the material of the cover in Bish is the same as that used by the Applicant. Therefore, the material of metal, including copper, inherently meets the claim limitation. "Products of identical chemical composition cannot have mutually exclusive properties." A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. In re Spada,911 F.2d 705, 709, 15 USPQ2d 1655 (Fed.Cir.1990).
Regarding claim 13, Kaneda teaches in figure 3 an electronic component mounting substrate (60).
Kaneda does not teach a cover with a material.
However, Bish teaches in figure 1 a cover (16) with a material (Col. 3, lines 57-62; wherein the lid can be several materials, including a metal like copper).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate of Kaneda to include a cover with a material chosen in order to provide high thermal conductivity (Bish Col. 3, lines 57-62).
Bish fails to explicitly teach “a material having a Young's modulus of 150 GPa or more”. However, the material of the cover in Bish is the same as that used by the Applicant. Therefore, the material of metal, including copper, inherently meets the claim limitation. "Products of identical chemical composition cannot have mutually exclusive properties." A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. In re Spada,911 F.2d 705, 709, 15 USPQ2d 1655 (Fed.Cir.1990).
Regarding claim 14, Kaneda teaches in figure 3 an electronic component mounting substrate (60).
Kaneda does not teach a cover with a material.
However, Bish teaches in figure 1 a cover (16) with a material (Col. 3, lines 57-62; wherein the lid can be several materials, including a metal like copper).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate of Kaneda to include a cover with a material chosen in order to provide high thermal conductivity (Bish Col. 3, lines 57-62).
Bish fails to explicitly teach “a material having a Young's modulus of 190 GPa or more”. However, the material of the cover in Bish is the same as that used by the Applicant. Therefore, the material of metal, including copper, inherently meets the claim limitation. "Products of identical chemical composition cannot have mutually exclusive properties." A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. In re Spada,911 F.2d 705, 709, 15 USPQ2d 1655 (Fed.Cir.1990).
Regarding claim 15, Kaneda teaches in figure 3 an electronic component mounting substrate (60).
Kaneda does not teach a cover is formed of a metal.
However, Bish teaches in figure 1 a cover (16) is formed of a metal (Col. 3, lines 57-62; wherein the lid can be a metal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate of Kaneda to include a cover formed of metal, in order to provide high thermal conductivity (Bish Col. 3, lines 57-62).
Regarding claim 16, Kaneda teaches in figure 3 an electronic component mounting substrate (60).
Kaneda does not teach a cover comprises a metal.
However, Bish teaches in figure 1 a cover (216) comprises a metal (Col. 3, lines 57-62; wherein the lid can be a metal).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate of Kaneda to include a cover comprised of metal, in order to provide high thermal conductivity (Bish Col. 3, lines 57-62).
Regarding claim 17, Kaneda teaches an electronic component mounting substrate (Fig 3; 60), wherein the upper build-up part (Fig 1A; layers 50-56) includes a plurality of conductor layers (Fig 1A; layers 50, 52, 54, 56) and a plurality of resin insulating layers (Fig 1A; layers 51, 53, 55) including the uppermost resin insulating layer and each not containing a reinforcing material (Fig 1A; [0078]; layers 51, 53, and 55 are able to be made of only resin), and the lower build-up part (Fig 1A; layers 31-36) includes a plurality of conductor layers (Fig 1A; layers 32, 34, 36) and a plurality of resin insulating layers (layers 31, 33, 35) including the lowermost resin insulating layer and each comprising a reinforcing material (Fig 1A; [0058]; layers 31, 33, and 35 may contain a filler in the resin).
Claim(s) 5 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaneda (US 20150102510 A1) in view of Bish (US 6906413 B2), as applied to claims 1-4 and 8-17 above, and further in view of Sakamoto (US 20190098752 A1).
Regarding claim 5, a modified Kaneda teaches an electronic component mounting substrate (Fig 3; 60) with an upper build-up part (Fig 1A; layers 50-56) and a lower build-up part (Fig 1A; layers 31-36).
A modified Kaneda does not teach a middle build-up part formed between the upper build-up part and the lower build-up part and comprising a middle resin insulating layer such that the middle resin insulating layer does not contain a reinforcing material.
However, Sakamoto teaches in figure 2 a middle build-up part (60) formed between the upper build-up part (70) and the lower build-up part (50F) and comprising a middle resin insulating layer (50) such that the middle resin insulating layer does not contain a reinforcing material ([0016]; 50 is only made of resin).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring board of Kaneda to include a middle build-up part, in order to relieve stress between the lower and upper build-up layers (Sakamoto [0026]).
Regarding claim 18, a modified Kaneda teaches an electronic component mounting substrate (Kaneda Fig 3; 60) with an upper build-up part (Fig 1A; layers 50-56) and a lower build-up part (Fig 1A; layers 31-36).
A modified Kaneda does not teach a middle build-up part formed between the upper build-up part and the lower build-up part and comprising a middle resin insulating layer such that the middle resin insulating layer does not contain a reinforcing material.
However, Sakamoto teaches in figure 2 a middle build-up part (60) formed between the upper build-up part (70) and the lower build-up part (50F) and comprising a middle resin insulating layer (50) such that the middle resin insulating layer does not contain a reinforcing material ([0016]; 50 is only made of resin).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring board of Kaneda to include a middle build-up part, in order to relieve stress between the lower and upper build-up layers (Sakamoto [0026]).
Claim(s) 6, 7, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaneda (US 20150102510 A1) in view of Bish (US 6906413 B2) and in view of Sakamoto (US 20190098752 A1), as applied to claims 5 and 18 above, and further in view of Ishihara (US 20170317017 A1).
Regarding claim 6, a modified Kaneda teaches an electronic component mounting substrate (Kaneda Fig 3; 60), wherein the upper build-up part (Kaneda Fig 1A; layers 50-56) includes a plurality of conductor layers (Kaneda Fig 1A; layers 50, 52, 54, 56) and a plurality of resin insulating layers (Kaneda Fig 1A; layers 51, 53, 55) including the uppermost resin insulating layer and each not containing a reinforcing material (Kaneda Fig 1A; [0078]; layers 51, 53, and 55 are able to be made of only resin), the middle build-up part (Sakamoto Fig 2; 60) includes a plurality of conductor layers (Sakamoto Fig 2; 58) and a plurality of resin insulating layers (Sakamoto Fig 2; 50) including the middle resin insulating layer (Sakamoto [0062]; wherein the middle build up part has at least one resin insulating layer and at least one conductor layer) and each not containing a reinforcing material (Sakamoto [0016]; 50 is only made of resin), and the lower build-up part (Kaneda fig 1A; layers 31-36) includes a plurality of conductor layers (Kaneda Fig 1A; layers 32, 34, 36) and a plurality of resin insulating layers (Kaneda Fig 1A; layers 31, 33, 35) including the lowermost resin insulating layer and each comprising a reinforcing material (Kaneda Fig 1A; [0058]; layers 31, 33, and 35 may contain a filler in the resin).
A modified Kaneda does not teach a reinforcing material including a fiber.
However, Ishihara teaches in figure 1 a reinforcing material including a fiber ([0028]; wherein each resin insulating layer 11a, 11b, and 11c can be formed differently and may include a glass fiber).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the resin insulating layer of Kaneda to include fiber in the reinforcing material, in order to improve mechanical strength and insulation ability.
Regarding claim 7, a modified Kaneda teaches electronic component mounting substrate (Kaneda Fig 3; 60) wherein the insulating (layers 31, 33, 35) and conductor (layers 32, 34, 36) layers of a lower build-up part (layers 31-36) have a greater thickness than the insulating (51, 53, 55) and conductor (50, 52, 54, 56) layers of an upper build-up (layers 50-56) part (Fig 1A; [0079]; wherein the insulating layers 51, 53, and 55 are thinner than the insulating layers in structure 11, such as 31, 33, and 35; and the conductor layers 50, 52, 54, and 56 are thinner than the conductor layers of structure 11, such as 32, 34, and 36).
A modified Kaneda does not teach a middle build-up part wherein the upper, middle, and lower build-up parts are formed such that each of the resin insulating layers in the lower build-up part has a thickness that is greater than a thickness of each of the resin insulating layers in the middle build-up part, the thickness of each of the resin insulating layers in the middle build-up part is greater than a thickness of each of the resin insulating layers in the upper build-up part, each of the conductor layers in the lower build-up part has a thickness that is greater than a thickness of each of the conductor layers in the middle build-up part, and the thickness of each of the conductor layers in the middle build-up part is greater than a thickness of each of the conductor layers in the upper build-up part.
However, Sakamoto teaches in figure 2 a middle build-up part (60) wherein the upper (70), middle, and lower (50F) build-up parts are formed such that each of the resin insulating layers in the lower build-up part (layers 150F) has a thickness (a1) that is greater than a thickness (a2) of each of the resin insulating layers in the middle build-up part ([0062]; 50; wherein the middle build up part has at least one resin insulating layer), the thickness of each of the resin insulating layers in the middle build-up part is greater than a thickness (a3) of each of the resin insulating layers (layers 170F) in the upper build-up part ([0040] to [0043]; wherein a1 is greater than a2 and a2 is greater than a3), each of the conductor layers in the lower build-up part (layers 158F) has a thickness (b1) that is greater than a thickness (b2) of each of the conductor layers in the middle build-up part ([0062]; 58; wherein the middle build up part has at least one conductor layer), and the thickness of each of the conductor layers in the middle build-up part is greater than a thickness (b3) of each of the conductor layers (layers 178F) in the upper build-up part ([0028]; wherein b1 is greater than b2 and b2 is greater than b3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a middle build-up part and differing thicknesses in the layers of each build-up part to the board of Kaneda, in order to accommodate the different magnitudes of stresses per unit cross-sectional area across the different layers of the wiring board (Sakamoto [0028] and [0044]).
Regarding claim 19, a modified Kaneda teaches an electronic component mounting substrate (Kaneda Fig 3; 60), wherein the upper build-up part (Kaneda Fig 1A; layers 50-56) includes a plurality of conductor layers (Kaneda Fig 1A; layers 50, 52, 54, 56) and a plurality of resin insulating layers (Kaneda Fig 1A; layers 51, 53, 55) including the uppermost resin insulating layer and each not containing a reinforcing material (Kaneda Fig 1A; [0078]; layers 51, 53, and 55 are able to be made of only resin), the middle build-up part (Sakamoto Fig 2; 60) includes a plurality of conductor layers (Sakamoto Fig 2; 58) and a plurality of resin insulating layers (Sakamoto Fig 2; 50) including the middle resin insulating layer (Sakamoto [0062]; wherein the middle build up part has at least one resin insulating layer and at least one conductor layer) and each not containing a reinforcing material (Sakamoto [0016]; 50 is only made of resin), and the lower build-up part (Kaneda fig 1A; layers 31-36) includes a plurality of conductor layers (Kaneda Fig 1A; layers 32, 34, 36) and a plurality of resin insulating layers (Kaneda Fig 1A; layers 31, 33, 35) including the lowermost resin insulating layer and each comprising a reinforcing material (Kaneda Fig 1A; [0058]; layers 31, 33, and 35 may contain a filler in the resin).
A modified Kaneda does not teach a reinforcing material including a fiber.
However, Ishihara teaches in figure 1 a reinforcing material including a fiber ([0028]; wherein each resin insulating layer 11a, 11b, and 11c can be formed differently and may include a glass fiber).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the resin insulating layer of Kaneda to include fiber in the reinforcing material, in order to improve mechanical strength and insulation ability.
Regarding claim 20, a modified Kaneda teaches electronic component mounting substrate (Kaneda Fig 3; 60) wherein the insulating (layers 31, 33, 35) and conductor (layers 32, 34, 36) layers of a lower build-up part (layers 31-36) have a greater thickness than the insulating (51, 53, 55) and conductor (50, 52, 54, 56) layers of an upper build-up (layers 50-56) part (Fig 1A; [0079]; wherein the insulating layers 51, 53, and 55 are thinner than the insulating layers in structure 11, such as 31, 33, and 35; and the conductor layers 50, 52, 54, and 56 are thinner than the conductor layers of structure 11, such as 32, 34, and 36).
A modified Kaneda does not teach a middle build-up part wherein the upper, middle and lower build-up parts are formed such that each of the resin insulating layers in the lower build-up part has a thickness that is greater than a thickness of each of the resin insulating layers in the middle build-up part, the thickness of each of the resin insulating layers in the middle build-up part is greater than a thickness of each of the resin insulating layers in the upper build-up part, each of the conductor layers in the lower build-up part has a thickness that is greater than a thickness of each of the conductor layers in the middle build-up part, and the thickness of each of the conductor layers in the middle build-up part is greater than a thickness of each of the conductor layers in the upper build-up part.
However, Sakamoto teaches in figure 2 a middle build-up part (60) wherein the upper (70), middle and lower (50F) build-up parts are formed such that each of the resin insulating layers in the lower build-up part (layers 150F) has a thickness (a1) that is greater than a thickness (a2) of each of the resin insulating layers in the middle build-up part ([0062]; 50; wherein the middle build up part has at least one resin insulating layer), the thickness of each of the resin insulating layers in the middle build-up part is greater than a thickness (a3) of each of the resin insulating layers (layers 170F) in the upper build-up part ([0040] to [0043]; wherein a1 is greater than a2 and a2 is greater than a3), each of the conductor layers in the lower build-up part (layers 158F) has a thickness (b1) that is greater than a thickness (b2) of each of the conductor layers in the middle build-up part ([0062]; 58; wherein the middle build up part has at least one conductor layer), and the thickness of each of the conductor layers in the middle build-up part is greater than a thickness (b3) of each of the conductor layers (layers 178F) in the upper build-up part ([0028]; wherein b1 is greater than b2 and b2 is greater than b3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a middle build-up part and differing thicknesses in the layers of each build-up part to the board of Kaneda, in order to accommodate the different magnitudes of stresses per unit cross-sectional area across the different layers of the wiring board (Sakamoto [0028] and [0044]).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Chung (US 6409859 B1), Morita (US 20140353022 A1), and Ishihara (US 20170263571 A1).
Chung teaches a wiring substrate and electronic component attached to a metal cover.
Morita teaches a printed wiring board attached to an electronic component, wherein the board has resin insulating layers and conductor layers of differing thicknesses.
Ishihara teaches a wiring board with insulating resin and conductor layers and electronic components encapsulated by a thick cover.
The above references are considered of particular relevance to the claimed invention but cannot
be considered to teach the limitations or combined to being obvious to a person skilled in the art to
disclose the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABIGAIL MARIE THAYER whose telephone number is (571)270-0134. The examiner can normally be reached M-Th/F 7:30-5:00.
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/ABIGAIL MARIE THAYER/Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
