DETAILED ACTION
Status of Claims
The status of the claims is as follows:
(a) Claims 1-20 remain pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is not directed to patent eligible subject matter. Specifically, the claimed invention is directed to a judicial exception without significantly more.
Analysis for Independent Claims 1, 14, and 18:
Step 1: Determining if claim(s) are directed a statutory class of invention (i.e., process, machine, manufacture, or composition of matter).
Independent claims 1, 14, and 18 are directed to statutory categories. (Step 1: yes)
Step 2A Prong One: Determining if the claim(s) recite a judicial exception (e.g., mathematical concepts, certain method of organizing human activity, or a mental processes (MPEP 2106.04).
The independent claims recite a judicial exception under the category of mental processes. Specifically, the claims detail a series of steps that include receiving a command, determining addresses based on a floating-point index, accessing values, calculating weights, and producing an interpolated value. Each of these steps can be performed in the human mind, or by a human using a pen and paper. The claim language does not specify any particular machinery or physical transformation beyond the general use of a memory array and a memory controller, which are standard components used in a wide range of computing processes.
Claim 1 describes the memory controller's operation in receiving a command and determining addresses for data values. This determination is a conceptual process that can be performed mentally. Accessing the first and second values from the memory array, as well as determining the respective weights for these values, involves generic mathematical calculations. The concluding step of providing an interpolated value is also an abstract mathematical concept.
Claim 14 pertains to a non-transitory machine-readable medium that stores instructions to perform similar operations as claim 1. Despite the reference to a machine-readable medium, the underlying process remains an abstract idea. The operations described by the instructions are processes that could be executed by a human mind, which are indicative of a mental process.
Claim 18 asserts a method that encompasses the same abstract ideas as the previous claims. The method comprises steps for receiving data and performing mathematical operations to derive an interpolated value. The claim does not impart any inventive technology or concrete application, instead reciting a sequence of steps that can be performed in the human mind, reflecting a mental process.
As a result, the independent claims as presented are directed to a judicial exception of a mental process.
Step 2A Prong Two: Determining if additional limitations within the claim(s) integrate the judicial exception into a practical application.
Claim 1 specifies the use of a memory array and a memory controller, which are standard components in the field of computing. However, these components are employed only in their most basic function to perform operations that are intrinsically tied to mathematical concepts and mental processes, such as determining values based on indices and weights, and computing an interpolated value. The claim does not introduce a particular inventive technology or novel application of these components; it merely invokes generic computer functions that do not impose any meaningful limits on the use of the abstract idea.
Claim 14 references a non-transitory machine-readable medium containing instructions that, when executed, perform the same operations as Claim 1. While this claim technically ties the judicial exception to a specific machine, the medium itself does not contribute to an inventive concept that transforms the abstract idea into a practical application. The instructions encoded on the medium perform generic computer functions that do not extend beyond the abstract idea itself. The claim lacks any specific implementation details or technological improvements that would integrate the judicial exception into a practical application.
Claim 18 outlines a method comprising steps that are effectively the same as those in Claims 1 and 14. It is a process claim that articulates the abstract idea of manipulating data to produce an interpolated value. The method claim, like the others, does not include additional elements that work in conjunction with the judicial exception to transform the process into a practical application. The steps described are routine data manipulation operations that could be executed by a generic computer without any inventive concept or application to a particular field or technology.
As a result, the Examiner finds the independent claims, as currently presented, fail to incorporate limitations that would qualify as significantly more than the judicial exception itself. They do not apply the judicial exception in a way that reflects an improvement in the functioning of a computer or an effect that applies beyond the abstract idea of manipulating data.
Step 2B: Determining if the additional elements, taken individually and in combination, do not result in the claim, as a whole, amounting to significantly more than the judicial exception.
Claim 1 specifies a memory array and a memory controller. These are standard elements in computing technology and, even when taken in combination with the steps of receiving a command and producing an interpolated value, they do not contribute to an inventive concept that elevates the claim beyond a mere instruction to implement an abstract idea on a computer. The functions of the memory array and memory controller are well-understood, routine, and conventional activities previously known to the industry.
In Claim 14, the additional element is a non-transitory machine-readable medium. This element does not add meaningful limits to the process of determining interpolated values from an array of data. The medium itself is a generic carrier for the instructions that embody the abstract idea. It does not enhance the mathematical concept or mental process in such a way that it amounts to an inventive concept. The instructions it carries out are abstract processes that remain untethered to any specific machine or transformation.
Claim 18 is a method claim that involves steps for executing a data manipulation process. The steps of the method, even when considered as an ordered combination, do not add anything of significance to the judicial exception. They do not apply or use the judicial exception in a way that leads to an improvement in another field or the functioning of the computer itself. The claim merely instructs to apply the abstract idea in a generic computer environment without any inventive means or methods that would amount to significantly more than the abstract idea.
Therefore, each claim, taken as a whole, does not contain additional elements that transform the nature of the claim into an inventive application of the judicial exception.
Conclusion:
The independent claim(s) are directed to the abstract idea of a mental process. Accordingly, claims 1, 14, and 18 are not patent eligible under 35 U.S.C. 101.
Analysis for Dependent Claims 2-13, 15-17, and 19-20:
Step 1: Determining if the claim(s) are directed a statutory class of invention (i.e., process, machine, manufacture, or composition of matter).
The dependent claims are properly directed to claims 1, 14, and 18. As a result, the dependent claims are properly directed to statutory classes. (Step 1: yes)
Step 2A Prong One: Determining if the claim(s) recite a judicial exception (e.g., mathematical concepts, mental processes, certain methods of organizing human activity, fundamental economic practices, and “an idea ‘of itself’”).
The dependent claims continue to encompass the mental process established in the independent claim(s). The same analysis of Step 2A Prong One for the independent claim(s) applies. Therefore, the dependent claims are directed to the judicial exception of a mental process.
Step 2A Prong Two: Determining if additional limitations within the claim(s) integrate the judicial exception into a practical application.
The dependent claims recite additional limitations, these limitations, when viewed both individually and in combination for the claim, fail to integrate the judicial exception into a practical application. As a result, the dependent claims are not integrated into a practical application.
Step 2B: Determining if the additional elements, taken individually and in combination, do not result in the claim, as a whole, amounting to significantly more than the judicial exception.
The additional elements in the dependent claims fail to recite any additional elements, viewed both individually (i.e., within a claim) and as a whole (i.e., claim set), that amount to significantly more than the judicial exception. The same analysis applies in this step 2B as discussed in Step 2A Prong Two (see independent claim analysis). As a result, the dependent claims fail to claim anything significantly more than the judicial exception and fail to integrate said claims into a practical application.
Conclusion:
The dependent claims are directed to the abstract idea of a mental process. Accordingly, claims 1-20 are not patent eligible.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Emmart U.S. P.G. Publication 2021/0064338 (hereinafter, Emmart), in view of Henry et al. U.S. P.G. Publication 2018/0189639 (hereinafter, Henry).
Regarding Claim 1, Emmart describes a system comprising:
-a memory array (memory array (e.g., GDDR5), Emmart, Paragraphs 0130 and 0237 and Figures 15B, 18A, 23-24, 27, and 29); and
-a memory controller coupled to the memory array and configured to perform operations (memory controller coupled to memory and can perform operations, Emmart, Paragraph 0376, 0277, and 0237 and Figures 15B, 18A, 23-24, 27, and 29), comprising:
-receiving, via a bus, a command comprising a floating-point index into an integer-indexed array of values stored in the memory array (memory controller can issue a command for indexing or storing floating point values into an array of memory, Emmart, Paragraphs 0277-0288 and Figures 15B, 18A, 23-24, 27, and 29);
-determining, based on the floating-point index, a first address of a first value of the integer-indexed array of values and a second address of a second value of the array of values (overall processing system would know a first address of a first value of the array of values (e.g., a location for a value) and a second address of a second value within an array of values (e.g., a second location for some value, Emmart, Paragraphs 0236-0237 and Figures 15B, 18A, 23-24, 27, and 29);
-accessing, from the memory array, the first value from the first address and the second value from the second address (capable of accessing the values from the memory array, values accessed can be the first value at a first address and a second value at a second memory address, Emmart, Paragraphs 0236-0237 and Figures 15B, 18A, 23-24, 27, and 29);
…
-providing, in response to the command, the interpolated value (providing for an interpolated value, Emmart, Paragraph 0426).
Henry does not specifically disclose the system to include determining, based on the first weight for the first value, the first value, a second weight for the second value, and the second weight, an interpolated value.
Henry discloses, teaches, or at least suggests the missing limitation(s). Henry describes a memory system that is capable of determining both weight values and applying said weight values to other values stored in floating-point index memory arrays (Henry, Paragraphs 0110-0130)
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the system of Emmart to include determining, based on the first weight for the first value, the first value, a second weight for the second value, and the second weight, an interpolated value, as disclosed, taught, or at least suggested by Henry.
It would have been obvious to combine and modify the cited references, with a reasonable expectation of success because storing, determining, and accessing memory values in the limitations stated above allow for improved performance and efficiently in computing / data accessing (Henry, Paragraph 0003).
Regarding Claim 2, Emmart, as modified, describes the system of claim 1, further comprising: circuits to control a vehicle (autonomous vehicle, Emmart, Paragraph 0100 and Figure 10A); and one or more processing elements configured to perform operations comprising: using the interpolated value to generate an image from synthetic aperture radar (SAR) pulse data (processing values from images generated by a variety of sensors, like radar pulse data, Emmart, Paragraphs 0110-00120 and 0144-0148); providing the image to a trained machine learning model; and using a result from the trained machine learning model to generate inputs to the circuits to control the vehicle (machine learning with data, Emmart, Paragraphs 0144-0148).
Regarding Claim 3, Emmart, as modified, describes the system of claim 2, wherein: the one or more processing elements are further configured to cause interpolated values for generation of the image to be determined by multiple memory controllers connected in a hybrid threading fabric (hybrid threading fabric, Emmart, Paragraphs 0235, 0276).
Regarding Claim 4, Emmart, as modified, describes the system of claim 1, wherein:
the bus is part of a network on chip (NOC); and the command is received from a host processor (network on a chip and commands can be received by a host processor, Emmart, Paragraph 0142 and Figures 15B, 18A, 23-24, 27, and 29).
Regarding Claim 5, Emmart, as modified, describes the system of claim 1, wherein the providing of the interpolated value comprises providing the interpolated value via a network on chip (NOC) hub edge to a hybrid threading processor (HTP) (interpolated values, via network on a chip, using a hybrid threading processor and process, Emmart, Paragraphs 0426-0429).
Regarding Claim 6, Emmart, as modified, describes the system of claim 1, wherein the memory controller is a memory controller chiplet of a computer near memory (CNM) system (memory controller is a computer near memory, Emmart, Figures 15B, 18A, 23-24, 27, and 29).
Regarding Claim 7, Emmart, as modified, describes the system of claim 1, wherein:
the system further comprises a cache memory (cache memory, Emmart, Paragraph 0077 and 0325); and the operations further comprise:
receiving, prior to the receiving of the command, a second command that indicates an address of a beginning of the array of values and a number of values in the array of values; and in response to the second command, storing the address and the number of values in the cache memory (via a command, storing values at an address, wherein the address is the start of an array, Emmart, Paragraphs 0236-0237, 0077, and 0325 and Figures 15B, 18A, 23-24, 27, and 29).
Regarding Claim 8, Emmart, as modified, describes the system of claim 1, wherein:
the received command is a single instruction/multiple data (SIMD) command that comprises multiple floating-point indices into multiple arrays of values stored in the memory array, the multiple floating-point indices comprising the floating-point index (SIMD commands, multiple floating point data handling in multiple arrays of memory, Emmart, Paragraph 0321 and Figure 20C).
Regarding Claim 9, Emmart, as modified, describes the system of claim 8, wherein:
the SIMD command is pipelined such that at least one of the multiple floating-point indices is processed each clock cycle (SIMD architecture is to handle a floating point index per clock cycle, Emmart, Paragraphs 0321-0324 and Figure 20C).
Regarding Claim 10, Emmart, as modified, describes the system of claim 1, wherein:
the floating-point index has a value between a first integer index of the array of values and a second integer index of the array of values; and the first address corresponds to the first integer index and the second address corresponds to the second integer index (storing values following a floating point index system that corresponds to integer index of the array of values, wherein the integer index values can be stored at a first address and a second address, Emmart, Paragraph 0286-0291 and Figures 15B, 18A, 23-24, 27, and 29).
Regarding Claim 11, Emmart, as modified, describes the system of claim 10, wherein the operations further comprise: performing bounds-checking on the floating-point index (setting bound checking for floating point indexes, Emmart, Paragraph 0064).
Regarding Claim 12, Emmart, as modified, describes the system of claim 11, wherein:
the first number of bits is 64 bits; and the second number of bits is 32 bits (64 bits and 32 bits used, Emmart, Paragraphs 0072 and 0430).
Regarding Claim 13, Emmart, as modified, describes the system of claim 1.
Henry does not specifically disclose the system to include determining of the interpolated value comprises: determining a first product of the first value with the first weight; determining a second product of the second value with the second weight; and determining the interpolated value as a sum of the first product and the second product.
Henry discloses, teaches, or at least suggests the missing limitation(s). Henry describes a memory system that is capable of determining both weight values and applying said weight values to other values stored in floating-point index memory arrays (Henry, Paragraphs 0110-0130).
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the system of Emmart to include determining of the interpolated value comprises: determining a first product of the first value with the first weight; determining a second product of the second value with the second weight; and determining the interpolated value as a sum of the first product and the second product, as disclosed, taught, or at least suggested by Henry.
It would have been obvious to combine and modify the cited references, with a reasonable expectation of success because storing, determining, and accessing memory values in the limitations stated above allow for improved performance and efficiently in computing / data accessing (Henry, Paragraph 0003).
Regarding Claim 14, Emmart describes a non-transitory machine-readable medium that stores instructions that, when executed by a system, cause the system to perform operations (memory controller coupled to memory and can perform operations, Emmart, Paragraph 0376, 0277, and 0237 and Figures 15B, 18A, 23-24, 27, and 29) comprising:
-receiving, via a bus, a command comprising a floating-point index into an integer-indexed array of values stored in a memory array (memory controller can issue a command for indexing or storing floating point values into an array of memory, Emmart, Paragraphs 0277-0288 and Figures 15B, 18A, 23-24, 27, and 29);
-determining, based on the floating-point index, a first address of a first value of the integer-indexed array of values and a second address of a second value of the integer-indexed array of values (overall processing system would know a first address of a first value of the array of values (e.g., a location for a value) and a second address of a second value within an array of values (e.g., a second location for some value, Emmart, Paragraphs 0236-0237 and Figures 15B, 18A, 23-24, 27, and 29);
-accessing, from the memory array, the first value from the first address and the second value from the second address (capable of accessing the values from the memory array, values accessed can be the first value at a first address and a second value at a second memory address, Emmart, Paragraphs 0236-0237 and Figures 15B, 18A, 23-24, 27, and 29);
…
-providing, in response to the command, the interpolated value (providing for an interpolated value, Emmart, Paragraph 0426)..
Henry does not specifically disclose the medium to include determining, based on the floating-point index, a first weight for the first value and a second weight for the second value; determining, based on the first weight, the first value, the second weight, and the second value, an interpolated value.
Henry discloses, teaches, or at least suggests the missing limitation(s). Henry describes a memory system that is capable of determining both weight values and applying said weight values to other values stored in floating-point index memory arrays (Henry, Paragraphs 0110-0130)
As a result, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to modify the medium of Emmart to include determining, based on the floating-point index, a first weight for the first value and a second weight for the second value; determining, based on the first weight, the first value, the second weight, and the second value, an interpolated value, as disclosed, taught, or at least suggested by Henry.
It would have been obvious to combine and modify the cited references, with a reasonable expectation of success because storing, determining, and accessing memory values in the limitations stated above allow for improved performance and efficiently in computing / data accessing (Henry, Paragraph 0003).
Regarding Claim 15, the Applicant’s claim has similar limitations to claim 6 and therefore are rejected for similar reasons set forth by the Examiner in the rejection of said claim.
Regarding Claim 16, the Applicant’s claim has similar limitations to claim 2 and therefore are rejected for similar reasons set forth by the Examiner in the rejection of said claim.
Regarding Claim 17, the Applicant’s claim has similar limitations to claim 7 and therefore are rejected for similar reasons set forth by the Examiner in the rejection of said claim.
Regarding Claim 18, the Applicant’s claim has similar limitations to claim 1 and therefore are rejected for similar reasons set forth by the Examiner in the rejection of said claim.
Regarding Claim 19, the Applicant’s claim has similar limitations to claim 2 and therefore are rejected for similar reasons set forth by the Examiner in the rejection of said claim.
Regarding Claim 20, the Applicant’s claim has similar limitations to claim 3 and therefore are rejected for similar reasons set forth by the Examiner in the rejection of said claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW J CROMER whose telephone number is (313)446-6563. The examiner can normally be reached M-F: ~ 8:15 A.M. - 6:00 P.M..
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/ANDREW J CROMER/Examiner, Art Unit 3667