DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 8, 9, 12, are rejected under 35 U.S.C. 103 as being unpatentable over Granger-Jones (US-20230188096-A1) in view of Zhang (CN-107332522-A).
Regarding claim 1: Granger-Jones, Fig. 1, discloses a low-noise amplifier, LNA ((100), ¶[0005], lines 1-2), circuitry for amplifying an input signal at an input to an output signal at an output (LNA IN, LNA OUT);
the circuitry comprising; a first cascode amplifier (path 106) and a second complementary cascode amplifier (108), respectively connected to a first load (first inductor 116, ¶[0019]) and a second load (fourth inductor 128, ¶[0020]); wherein the first load (116) and the second load (128) are coupled (via capacitor (134), (¶[0021]) and wherein the output signal is an output (LNA OUT 104 via output node 130 and capacitor 132, ¶[0021]) of the first or second cascode amplifier (output node 130 associated with path 108 and coupled to drain 110D of path 106 through capacitor 134, ¶[0021]) ; wherein the first cascode amplifier (106) comprises: a first initial amplification stage (transistor 112), connected to the input (LNA IN 102 via input inductor 138 and capacitor 136 to gate 112G (¶[0022]) and to a lower power supply node (ground via source 112S and inductor 118; ¶([0019]); and a first transistor (transistor 110), arranged in a common-gate configuration (110), in cascode with the first initial amplification stage (110/112) and connected to the first load (first inductor 116) (¶[0019]); wherein the second cascode amplifier (108) comprises: a second initial amplification stage (transistor 120) , connected to the input (LNA IN 102 via input inductor 138 and capacitor 142 to gate 120G; ¶[0023]) and to a higher power supply node (Vcc via source 120S and inductor 126) (¶[0020]); a second transistor (transistor 122), arranged in a common-gate configuration (122), in cascode with the second initial amplification stage (122/120)) and connected to the second load ( inductor 128); (¶[0020]).
However, Granger-Jones does not disclose inputs of the first and second transistors are capacitively coupled such that the first and second transistors are connected at frequencies higher than a frequency characterising the capacitive coupling.
Zhang, Fig. 10, does disclose inputs of the first (intermediate node N4 of common-gate transistor M15) and second transistors (intermediate node N2 of common-gate transistor M17) are capacitively coupled (N4 and N2 are connected by capacitor C39) such that the first and second transistors are connected at frequencies (C39 implements an AC short circuit between the corresponding nodes) higher than a frequency characterising the capacitive coupling (capacitor C39, associated fifth-embodiment disclosure). Under the broadest reasonable interpretation, Zhang’s disclosure that C39 and C40 provide an AC short circuit between the corresponding nodes teaches the recited frequency-dependent connection, since the impedance of a capacitor decreases with increasing frequency such that the capacitively coupled nodes become effectively connected for AC signals above the characteristic frequency of the capacitive coupling.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the complementary cascode amplifier branches of Granger-Jones to include the capacitive coupling taught by Zhang between corresponding nodes of the complementary cascode branches, because such capacitive coupling provides an AC short circuit between the corresponding nodes, thereby improving performance of the LNA at high frequencies.
Regarding claim 3: Granger-Jones further, fig. 1, discloses wherein the first (110) and second (122) transistors respectively comprise a first gate terminal (gate of transistor 110) and a second gate terminal (gate of transistor 122).
Regarding claim 7: Granger-Jones, fig. 1, further discloses wherein the first and second loads each comprise an inductive coil (first inductor 116 and second inductor 128).
Regarding claim 8: Granger-Jones, fig. 1 does not disclose wherein the coils are inductively coupled, thereby coupling the first and second loads.
Granger-Jones, fig. 2, further discloses wherein the coils are inductively coupled, thereby coupling the first and second loads (inductively coupled inductors 216 and 228).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the first and second inductive loads of fig. 1 embodiment of Granger-Jones according to the inductively coupled load arrangement taught in fig. 2, in order to provide a more compact layout of the amplifier (¶[0026], lines 6-9, ¶[0033], lines 1-5).
Regarding claim 9: Granger-Jones , fig. 1, further discloses wherein the coils are capacitively coupled, thereby coupling the first (116) and second (128) loads (¶[0021]).
Regarding claim 12: Granger-Jones, fig. 1, further discloses comprising a coupling capacitor (capacitor (134)) for providing the capacitive coupling ((116), (128); ¶[0021]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Granger-Jones (US-20230188096-A1) in view of Zhang (CN-107332522-A) as applied to claim 1 above, and further in view of Sankaranarayanan (US-9178473-B2).
Regarding claim 2: Granger-Jones in view of Zhang further discloses wherein the first (112) and second (122) transistors.
However, Granger-Jones in combination with Zhang does not disclose wherein the transistors are configured to operate in a strong saturation region.
Sankaranarayanan teaches wherein the transistors are configured to operate in a strong saturation region (a cascode amplifier in which transistor (222) operates as a common-gate amplifier and is biased to operate in the saturation region¶[0041]-[0045]; applicant explains that “strong saturation region” may also be referred to as “saturation region”, (¶[0012])).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to configure the first and second common-gate cascode transistors of Granger-Jones in view of Zhang to operate in the saturation region, as taught by Sankaranarayanan, in order to provide high impedance at the drains of the cascode transistors and thereby achieve a high output impedance and mitigate loading effects.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Granger-Jones (US-20230188096-A1) in view of Zhang (CN-107332522-A) as applied to claim 1 above, and further in view of Naeini et al. (US 2017/0359040 A1).
Regarding claim 4: Granger-Jones in combination with Zhang do not disclose wherein the first gate terminal is connected to the higher power supply and wherein the second gate terminal is connected to the lower power supply.
Naeini, fig. 2, wherein the first gate terminal is connected to the higher power supply and wherein the second gate terminal is connected to the lower power supply (¶[0026]-[0028]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the complementary cascode amplifier of Granger-Jones in view of Zhang according to the gate-biasing arrangement taught by Naeini, by connecting the gate terminals to the higher and lower power supplies, in order to provide appropriate DC bias potentials to the common-gate transistors of the cascode amplifier.
Claims 5, 13, 14, 15, 16, 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Granger-Jones (US-20230188096-A1) in view of Zhang (CN-107332522-A) as applied to claim 1 above, and further in view of Dunworth et al. (US-10965261-B2).
Regarding claim 5: Granger-Jones in view of Zhang does not disclose wherein the first and second initial amplification stages each comprise a transistor, arranged in a common-source configuration.
Dunworth, Fig. 4B, discloses wherein the first (transistor 436) and second (transistor 440) initial amplification stages each comprise a transistor, arranged in a common-source configuration.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to configure the first and second initial amplification stages of Granger-Jones in combination with Zhang as, taught by Dunworth, in order to provide signal amplification.
Regarding claim 13: Granger-Jones in view of Zhang does not disclose further comprising an output amplifier, wherein the output signal is further applied to the output amplifier, thereby cascading the first and second cascode amplifiers with the output amplifier.
Dunworth, Fig. 4C, discloses an output amplifier (transistor 452), wherein the output signal (Vout) is further applied to the output amplifier (through matching network (454)), thereby cascading the first and second cascode amplifiers with the output amplifier.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the LNA circuitry of Granger-Jones in view of Zhang to further include an output amplifier as taught by Dunworth, in order to further amplify the output signal.
Regarding claim 14: Granger-Jones in view of Zhang in combination with Dunworth fig. 4C does not disclose wherein the output amplifier comprises an output transistor, arranged in a common-source configuration and connected to an output load.
Dunworth, fig. 8B, discloses wherein the output amplifier comprises an output transistor (first NMOS transistor M17), arranged in a common-source configuration (M17) and connected to an output load (output transformer TF5).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the output amplifier of Dunworth, fig. 4C, according to the output amplifier arrangement taught by Dunworth, Fig. 8B, by providing a common-source output transistor connected to an output load, in order to couple the output amplifier to an output transformer for providing an output signal to an antenna.
Regarding claim 15: Granger-Jones, fig. 1, wherein the output signal is the output (LNA OUT 104 via capacitor 132, ¶[0021]) of the first cascode amplifier (path 106 via drain 110D and capacitor 134, ¶[0021]).
Regarding claim 16: Granger-Jones in view of Zhang does not disclose wherein the output transistor is an N-channel metal oxide semiconductor, NMOS, transistor.
Dunworth, fig. 8B, further discloses wherein the output transistor is an N-channel metal oxide semiconductor, NMOS, transistor (first NMOS transistor M17).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the LNA circuitry of Granger-Jones in view of Zhang in further view of Dunworth to provide the output transistor as an NMOS transistor, in order to increase power-added efficiency.
Regarding claim 17: Granger-Jones , fig. 1, further discloses wherein the output signal (LNA OUT 104 via capacitor 132) is the output of the second cascode amplifier (path 108 via output node 130; ¶[0021]).
Regarding claim 18: Granger-Jones in view of Zhang, wherein the output transistor is a P-channel metal oxide semiconductor, PMOS, transistor.
Dunworth, fig. 4C, discloses wherein the output transistor is a P-channel metal oxide semiconductor, PMOS, transistor (first output transistor M17) (the non-complementary transistor configuration of the output amplifier stage may include one or more PMOS transistors (¶[0009].
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the LNA circuitry of Granger-Jones in view of Zhang in further view of Dunworth to provide the output transistor of Dunworth, as a PMOS transistor, as taught by Dunworth, as a substitution of one expressly taught transistor type for another in the non-complementary output amplifier stage to provide output amplification with predictable results.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Granger-Jones (US-20230188096-A1) in view of Zhang (CN-107332522-A) as applied to claim 1 above, and further in view of Behera et al. (US-8310309-B2).
Regarding claim 6: Granger-Jones in view of Zhang does not disclose further comprising a first and a second pre-amplifier configured to pre-amplify the input signal and provide the so obtained pre-amplified input signal to the inputs of the first and second transistors respectively.
Behera, fig. 10, discloses further comprising a first (resistive feedback inverting amplifier 141) and a second (resistive feedback inverting amplifier 142) pre-amplifier configured to pre-amplify the input signal (differential input signal LNAINP, LNAINN) and provide the so obtained pre-amplified input signal (outputs 170,172) to the inputs of the first (gate of transistor 16 via capacitor 171) and second transistors respectively (gate of transistor 159 via capacitor 173).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the LNA circuitry of Granger-Jones in view of Zhang to include first and second pre-amplifiers as taught by Behera, in order to amplify the input signals prior to providing the amplified signals to the transistor inputs, thereby providing increased signal gain.
Claims 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Granger-Jones (US-20230188096-A1) in view of Zhang (CN-107332522-A) as applied to claim 1 above, and further in view of Sun (US-6476675-B1).
Regarding claim 10: Granger-Jones in view of Zhang does not disclose the first and second loads each comprise a capacitor.
Sun, fig. 2, discloses wherein the first and second loads each comprise a capacitor (positive output 110 and negative output 112 are each electrically connected to respective load capacitors 165 and 166; column 3, lines 55-59).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the first and second loads of Granger-Jones in view of Zhang according to the capacitive load arrangement taught by Sun, by providing respective load capacitors at the amplifier outputs, as a substitution of one known amplifier load arrangement for another to provide capacitive loading at the amplifier outputs with predictable results.
Regarding claim 11: Granger-Jones, fig. 1, discloses the first (116) and second (128) loads are capacitively coupled (capacitor (134)) (¶[0021]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Granger-Jones (US-20230188096-A1) in view of Zhang (CN-107332522-A) as applied to claim 1 above, and further in view of Koo et al. (US-20110304395-A1)
Regarding claim 19: Granger-Jones in view of Zhang does not disclose wherein the first cascode amplifier (first amplification section 110 comprising cascode-connected transistors MN1 and MN2) is directly connected to the input (RFIN is directly connected to the gate of transistor MN2).
Koo, fig. 1, discloses wherein the first cascode amplifier (amplification unit 111 comprising first NMOS amplifier MN1 and second NMOS amplifier MN2) is directly connected to the input (RFIN is directly connected to the gate of transistor MN2) (¶[0031], [0035]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the first cascode amplifier of Granger-Jones in view of Zhang according to the input arrangement taught by Koo, by directly providing the input signal to the input transistor of the cascode amplifier, in order to provide the input signal for amplification.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Granger-Jones (US-20230188096-A1) in view of Zhang (CN-107332522-A) as applied to claim 1 above, and further in view of Soe (US 9287836 B2).
Regarding claim 20: Granger-Jones in view of Zhang does not disclose wherein the second cascode amplifier is directly connected to the input.
Soe, fig. 4a, discloses wherein the second cascode amplifier is directly connected to the input (common-source transistor (M8) cascaded with a common-gate transistor (M7), wherein the input (in5) is provided to the gate of transistor M8 through inductor L14, which inductor L14 may be replaced by a short (column 6, lines 31-35)
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the second cascode amplifier of Granger-Jones in view of Zhang according to the input arrangement taught by Soe, by directly providing the input signal to the input transistor of the cascode amplifier, in order to provide the input signal for amplification.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Issakov et al. (US 9537457 B2) teaches a push-pull low-noise amplifier having complementary transistor stages arranged in common-gate configurations and capacitively coupled to an input for providing broadband input matching.
Omid-Zohoor (US 2015/0054581 A1) teaches a combination NMOS/PMOS amplifier including complementary amplifier sections and inductively coupled output circuitry for amplifying an input signal and providing an amplified output signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to /NATASHA Y MARANO/ whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NATASHA Y MARANO/Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
Prosecution Insights