DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 2/14/2026 have been fully considered but they are not persuasive.
Regarding the rejection of claims 1 & 16, the Applicant argues [Remarks: pg. 11, 2nd para. – pg. 12, 2nd last para.], that the combination of Lee and Im fails to teach the amended independent claims.
The Office respectfully disagrees.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The claim language does not explicitly define what an “array substrate” is. The array substrate could be the entire substrate that the display panel is formed on or is the array substrate only correspond to the display area of the display panel.
Further, the layer of the “same layer” is not explicitly claimed. For example, a layer would be the groupings of layers above the base substrate.
Further, the “side of the array substrate” is not explicitly claimed.
In both Lee and Im, the conductors corresponding to the claimed auxiliary electrodes are located above the top side of the base substrate. Conductor such as a connection wire utilized for connections would be above the base substrate on a same layer as the auxiliary electrodes.
Lee teaches in figure 6 a plurality of isolation structures, auxiliary electrodes 130 [utilized for supplying common voltages], that are divided into at least two groups.
Further refer to figure 4 of Im, which shows first common power line 310 corresponding to first area da1 and second common power line 320 corresponding to second area da2. Both first common power line 310 and second common power line 320 forming a comb like structure. The horizontal portion of the comb forming claimed first connection wire that connect each length of first common power line 310 together and utilized for connection to first voltage supply portion ps1 for a first grouping. The horizontal portion of the comb forming claimed first connection wire that connect each length of second common power line 320 together and utilized for connection to second voltage supply portion ps2 for a second grouping. An example of where the horizontal portion of the comb can be seen in figure 3 of Im corresponding to non-display area nda.
Thus, a person having ordinary skill in the art would know how to and where to place connection wires, such as placing such connection wires in the non-display areas of the display.
The first and second voltage supply portions ps1 and ps2 supplying different common voltages to different areas (first area da1 and second area da2), to improve display uniformity by reducing luminance deviation at different areas of the display [see para. 68-72 of Im].
Further, the Applicant states that “The common power line disclosed by Im is a conductive line designed to address wiring voltage drop, located on different layers” [Remarks: pg. 11, last para.], it is not different layers but different areas because the distance between the voltage supply and the pixels where the common voltages are applied in different areas have different path lengths, thus would have different resistances [which causes variations in voltage drop], which would cause variations in displayed images if not compensated for [see para. 6 of Im].
Thus, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the display driver circuit and the display panel of the display module of Lee, with the teachings of Im, to improve image quality by reducing luminance non-uniformity, as taught by Im [para. 84].
Regarding claim 16, refer to response to claim 1 above.
Thus, Lee as modified by Im teaches the amended independent claims 1 & 16.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-6 & 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190237527), in view of Im et al. (US 20220208934).
As to claim 1, Lee teaches a display module [abstract], comprising a display driver circuit (data driver) [para. 38] and a display panel (organic light-emitting display apparatus 1) [fig. 1 & para. 38], wherein
the display panel [figs. 1 & 3 & para. 38 & 60] comprises:
an array substrate (substrate 100) [figs. 1 & 3 & para. 60]; and
a plurality of isolation structures (auxiliary electrodes 130) [figs. 3 & 6 & para. 68-70] located on a side of the array substrate [fig. 3], wherein the isolation structure is conductive [figs. 3 & 6 & para. 69]; and the plurality of isolation structures are divided into at least two groups [fig. 6 & para. 102-103].
Lee does not explicitly teach the display driver circuit is an integrated circuit, and
the isolation structures in a same group are electrically connected to each other, and the isolation structures in different groups are electrically isolated from each other; and
a first connection wire disposed in a same layer as the plurality of isolation structures;
the display driver integrated circuit is connected to each group of the isolation structures respectively, the display driver integrated circuit is configured to provide independent common voltage for each group of the isolation structures based on a display brightness value command received, and the isolation structures in the same group are connected to each other or connected to the display driver integrated circuit through the first connection wire.
Im teaches the concept of a display module [abstract] that utilizes a display driver integrated circuit (source drive integrated circuit) [fig. 2 & para. 35, 58, 65, & 67] and a display panel (display panel dp) [figs. 1-3 & para. 35], wherein the display panel comprises:
an array substrate (first substrate 110) [figs. 1-2 & para. 36-37];
a plurality of isolation structures (first common power line 310 & second common power line 320) [figs. 3-8 & para. 39-42 & 56] located on a side of the array substrate, wherein the isolation structure is conductive (metal material) [para. 84]; and the plurality of isolation structures are divided into at least two groups (first display area da1 corresponding to first common power line 310 & second display area da2 corresponding to second common power line 320) [figs. 3-8 & para. 68-72, 78-79, 64, 144, & 159], the isolation structures in a same group are electrically connected to each other [figs. 5-6 & para. 68-72, 78-79, 64, 144, & 159], and the isolation structures in different groups are electrically isolated from each other [figs. 5-6 & para. 68-72, 78-79, 64, 144, & 159]; and
a first connection wire [figs. 1-2 & 5-6 & para. 68-72, 78-79, 64, 144, 146, & 159] disposed in a same layer as the plurality of isolation structures;
the display driver integrated circuit is connected to each group of the isolation structures respectively (source drive integrated circuit) [fig. 2 & para. 35, 58, 65, & 67], the display driver integrated circuit is configured to provide independent common voltage for each group of the isolation structures based on a display brightness value command received (data voltage determines current supplied to oled of pixel during image display. Each grouping of pixels utilizes different common voltage to compensate for voltage drop, the compensation improves uniformity of luminance) [fig. 3 & para. 53-55, 69-72, 76-77, & 47], and the isolation structures in the same group are connected to each other or connected to the display driver integrated circuit through the first connection wire [figs. 1-2 & 5-6 & para. 68-72, 78-79, 64, 144, 146, & 159].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the display driver circuit and the display panel of the display module of Lee, such that the display driver circuit is an integrated circuit, and the isolation structures in a same group are electrically connected to each other, and the isolation structures in different groups are electrically isolated from each other; and a first connection wire disposed in a same layer as the plurality of isolation structures; the display driver integrated circuit is connected to each group of the isolation structures respectively, the display driver integrated circuit is configured to provide independent common voltage for each group of the isolation structures based on a display brightness value command received, and the isolation structures in the same group are connected to each other or connected to the display driver integrated circuit through the first connection wire, as taught by Im, to improve image quality by reducing luminance non-uniformity, as taught by Im [para. 84].
As to claim 2, Lee as modified by Im teaches the display module according to claim 1, wherein the display panel further comprises:
a pixel defining layer (pixel-defining layer 120) [Lee: fig. 3 & para. 64-68] located between the array substrate and the plurality of isolation structures (between auxiliary electrode 130 & substrate 100) [Lee: fig. 3 & para. 64-68];
the pixel defining layer comprises a plurality of pixel openings (opening op1 formed between portions of cover portion 120c that start to concave inwardly) [Lee: fig. 3 & para. 64-65 & 89], an isolation opening is formed in the isolation structure (opening in auxiliary electrode 130 corresponding to distance d) [Lee: fig. 4 & para. 89], and an orthographic projection of the pixel opening on the array substrate is within an orthographic projection of the isolation opening on the array substrate (orthographic projection of opening op1 overlaps of plurality of pixel-defining layer 120 overlaps with orthographic projection of opening corresponding to auxiliary electrode 130 corresponding to distance d) [Lee: fig. 4 & para. 64-65 & 89].
As to claim 3, Lee as modified by Im teaches the display module according to claim 2, wherein the display panel further comprises:
a plurality of first electrodes (plurality of first pixel electrode 211) [Lee: figs. 2a-3 & para. 63-66] disposed with intervals;
the array substrate comprises a pixel driving circuit (pixel circuits pc) [Lee: figs. 2a-3 & para. 41-45 & 61];
wherein the first electrode is connected to the pixel driving circuit in the array substrate (first pixel electrode 211 to pixel circuit pc) [Lee: fig. 3];
the pixel defining layer is located on a side, away from the array substrate, of the first electrode, and the pixel opening exposes the first electrode (opening op1) [Lee: figs. 3 & 6]; and
a light-emitting material layer (first intermediate layer 221 emits light) [Lee: fig. 3 & para. 66] and a second electrode (counter electrode 231) [Lee: figs. 3-4 & 6 & para. 102] stacked in sequence are disposed in the pixel opening [Lee: fig. 3]; and
the second electrode extends from the pixel opening to be in electrical contact with the isolation structure (counter electrode 231 directly contact counter electrodes) [Lee: figs. 3-4 & 6 & para. 102].
As to claim 4, Lee as modified by Im teaches the display module according to claim 3, wherein the display panel further comprises a first inorganic encapsulation layer (first inorganic film 310 located on side of counter electrodes) [Lee: fig. 18 ¶. 146-147] located on a side, away from the array substrate, of the second electrode [Lee: fig. 18 ¶. 146-147].
As to claim 5, Lee as modified by Im teaches the display module according to claim 4, wherein at least a part of the first inorganic encapsulation layer extends, along a sidewall of the isolation structure facing the isolation opening, from an inner edge of the pixel opening to a side, away from the array substrate, of the isolation structure (first inorganic film 310) [Lee: fig. 18 ¶. 146-147].
As to claim 6, Lee as modified by Im teaches the display module according to claim 3, wherein at least two isolation structures of the plurality of isolation structures, respectively corresponding to pixel openings with light-emitting material layers emitting light of different colors (each of intermediate layers 221, 222, 223 correspond to different color) [Lee: para. 59, 76, 91 & Im: para. 146], are located in different groups (first display area da1 & second display area da2) [Im: figs. 5-6 & para. 68-72, 78-79, 64, 144, 146, & 159].
As to claim 16, Lee teaches a display module [abstract], comprising a display driver circuit (data driver) [para. 38] and a display panel (organic light-emitting display apparatus 1) [fig. 1 & para. 38], wherein
the display panel [figs. 1 & 3 & para. 38 & 60] comprises:
an array substrate (substrate 100) [figs. 1 & 3 & para. 60]; and
a plurality of pixel units [figs. 1-3 & para. 38-40] located on a side of the array substrate, wherein the plurality of pixel units are divided into at least two groups (each of intermediate layers 221, 222, 223 correspond to different color) [para. 59, 76, 91], the display driver circuit is connected to each group of the pixel units [figs. 1-3 & para. 38-40];
wherein each of the plurality of pixel unit comprises a first electrode (first pixel electrode 211) [figs. 2a-3 & para. 63-66], a light-emitting material layer (first intermediate layer 221 emits light) [fig. 3 & para. 66], and a second electrode (counter electrode 231) [figs. 3-4 & 6 & para. 102] stacked in sequence.
Lee does not explicitly teach the display driver circuit is an integrated circuit, and
the display driver integrated circuit is configured to provide independent common voltage for each group of the pixel units based on a display brightness value command received; and the second electrodes of a same group of the pixel units are connected to each other through connection wires disposed in a same layer as the plurality of pixel units.
Im teaches the concept of a display module [abstract] that utilizes a display driver integrated circuit (source drive integrated circuit) [fig. 2 & para. 35, 58, 65, & 67] and a display panel (display panel dp) [figs. 1-3 & para. 35],
wherein the display panel comprises:
an array substrate (first substrate 110) [figs. 1-2 & para. 36-37]; and
a plurality of pixel units (plurality of unit pixels up) [figs. 1-3 & para. 32] located on a side of the array substrate, wherein the plurality of pixel units are divided into at least two groups (first display area da1 corresponding to first common power line 310 & second display area da2 corresponding to second common power line 320) [figs. 3-8 & para. 68-72, 78-79, 64, 144, & 159], the display driver integrated circuit is connected to each group of the pixel units [para. 32], and the display driver integrated circuit (source drive integrated circuit) [fig. 2 & para. 35, 58, 65, & 67] is configured to provide independent common voltage for each group of the pixel units based on a display brightness value command received (data voltage determines current supplied to oled of pixel during image display. Each grouping of pixels utilizes different common voltage to compensate for voltage drop, the compensation improves uniformity of luminance) [fig. 3 & para. 53-55, 69-72, 76-77, & 47]; and a second electrodes of a same group of the pixel units are connected to each other through connection wires disposed in a same layer as the plurality of pixel units [figs. 1-2 & 5-6 & para. 68-72, 78-79, 64, 144, 146, & 159].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the display driver circuit and the display panel of the display module of Lee, such that the display driver circuit is an integrated circuit, and the display driver integrated circuit is configured to provide independent common voltage for each group of the pixel units based on a display brightness value command received; and a second electrodes of a same group of the pixel units are connected to each other through connection wires disposed in a same layer as the plurality of pixel units, as taught by Im, to improve image quality by reducing luminance non-uniformity, as taught by Im [para. 84].
As to claim 17, Lee as modified by Im teaches the display module according to claim 16, wherein the pixel unit comprises a first electrode (first pixel electrode 211) [Lee: figs. 2a-3 & para. 63-66], a light-emitting material layer (first intermediate layer 221 emits light) [Lee: fig. 3 & para. 66], and a second electrode (counter electrode 231) [Lee: figs. 3-4 & 6 & para. 102] stacked in sequence, the array substrate comprises a pixel driving circuit (pixel circuits pc) [Lee: figs. 2a-3 & para. 41-45 & 61], the first electrode is connected to the pixel driving circuit in the array substrate (first pixel electrode 211 to pixel circuit pc) [Lee: fig. 3], and the second electrode is connected to the display driver integrated circuit [Lee: fig. 1 & para. 38 & Im: fig. 2 & para. 35, 58, 65, & 67];
light-emitting material layers of the pixel units in a same group have a same light-emitting color (each of intermediate layers 221, 222, 223 correspond to different color, each of first display area da1 and second display area da2 have repeating colors) [Lee: para. 59, 76, 91 & Im: figs. 5-6 & para. 68-72, 78-79, 64, 144, 146, & 159], and light-emitting material layers of the pixel units in different groups have different light- emitting colors (each of intermediate layers 221, 222, 223 correspond to different color, each of first display area da1 and second display area da2 have different colors) [Lee: para. 59, 76, 91 & Im: figs. 5-6 & para. 68-72, 78-79, 64, 144, 146, & 159].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID TUNG whose telephone number is (571)270-3385. The examiner can normally be reached Monday-Friday; 10:00AM - 6:00PM.
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/DAVID TUNG/Primary Examiner, Art Unit 2622