Prosecution Insights
Last updated: July 17, 2026
Application No. 18/949,420

DISPLAY MODULE AND CONTROL METHOD THEREFOR, AND ELECTRONIC DEVICE

Non-Final OA §103
Filed
Nov 15, 2024
Priority
Dec 20, 2023 — CN 202311764506.5
Examiner
TUNG, DAVID
Art Unit
2622
Tech Center
2600 — Communications
Assignee
Kunshan Go-visionox Opto-electronics Co., Ltd.
OA Round
3 (Non-Final)
62%
Grant Probability
Moderate
3-4
OA Rounds
1y 3m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
361 granted / 581 resolved
At TC average
Strong +16% interview lift
Without
With
+16.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 12m
Avg Prosecution
21 currently pending
Career history
602
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
83.7%
+43.7% vs TC avg
§102
11.9%
-28.1% vs TC avg
§112
0.5%
-39.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 581 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/17/2026 has been entered. Response to Arguments Applicant's arguments filed 6/17/2026 have been fully considered but they are not persuasive. Regarding the rejection of claims 1 & 16, the Applicant argues [Remarks: pg. 10, 1st para. – pg. 11, last para.], that the combination of Lee as modified by Im fails to teach the amended claims. The Office respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “grouping isolation structures by color” & “the electrical common-voltage groups are defined by color” [Remarks: pg. 10, 1st para. – pg. 11, last para.]) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Referring to figures 3 & 6 of Lee, Lee teaches isolation structures, auxiliary electrodes 130 [function as lines supplying common power line, see para. 68-70 of Lee]. In figure 6, there are a plurality of auxiliary electrodes, each auxiliary electrode 130 corresponds to a horizontal row of pixels, the horizontal row of pixels utilizing repeating sequence of red [first intermediate layer 221 that emits red light corresponding to first counter electrode 231], green [second intermediate layer 222 that emits green light corresponding to second counter electrode 232], a blue [third intermediate layer 223 that emits blue light corresponding to third counter electrode 233]. Thus, Lee teaches light-emitting material layers of the pixel units in a same group have a same light-emitting color (each of intermediate layers 221, 222, 223 correspond to different color, each horizontal row having a same repeating same colors of red green blue), and light-emitting material layers of the pixel units in different groups have different light-emitting colors (each of intermediate layers 221, 222, 223 correspond to different color, each horizontal row having different colors of red green blue). Figure 4 of Im teaches further grouping multiple common lines together to form a first group of first common power line 310 corresponding to first area da1 that receives a first voltage supply portion ps1 and grouping multiple common lines together to form a second group of second common power line 320 second area da2 that receives a second voltage supply portion ps2. Im further teaches that the groupings can also be utilized along the horizontal direction [see para. 52 of Im]. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the display driver circuit and the display panel of the display module of Lee, with the teachings of Im, to improve image quality by reducing luminance non-uniformity, as taught by Im [para. 84]. Thus, as modified there would be a first grouping of isolating structures electrically connected to each other with repeating red, green, & blue pixels corresponding to a first area of a display [first area da1]; and a second grouping of isolating structures electrically connected to each other with repeating red, green, & blue pixels corresponding to a second area of the display [second area da2]. Each of the first grouping and the second grouping would be receiving different voltages [first area da1 receiving first voltage supply portion ps1 & second area da2 receiving second voltage supply portion ps2]. The first grouping of isolation structures having multiple repeating red, green, & blue pixels [different colors]. The second grouping of isolation structures having multiple repeating red, green, & blue pixels [different colors]. The first grouping of isolation structures associated with the grouping of first display area da1 and the second grouping of isolation structures associated with the grouping of the second display area da2. Thus, Lee as modified by Im teaches the amended claim limitation of wherein at least two isolation structures of the plurality of isolation structures, respectively corresponding to pixel openings with light-emitting material layers emitting light of different colors, are located in different groups. Thus, Lee as modified by Im teaches the amended independent claims as argued. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1, 4-5 & 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190237527), in view of Im et al. (US 20220208934). As to claim 1, Lee teaches a display module [abstract], comprising a display driver circuit (data driver) [para. 38] and a display panel (organic light-emitting display apparatus 1) [fig. 1 & para. 38], wherein the display panel [figs. 1 & 3 & para. 38 & 60] comprises: an array substrate (substrate 100) [figs. 1 & 3 & para. 60]; and a plurality of isolation structures (auxiliary electrodes 130) [figs. 3 & 6 & para. 68-70] located on a side of the array substrate [fig. 3], wherein the isolation structure is conductive [figs. 3 & 6 & para. 69]; and the plurality of isolation structures are divided into at least two groups [fig. 6 & para. 102-103]; a pixel defining layer (pixel-defining layer 120) [fig. 3 & para. 64-68] located between the array substrate and the plurality of isolation structures (between auxiliary electrode 130 & substrate 100) [fig. 3 & para. 64-68]; the pixel defining layer comprises a plurality of pixel openings (opening op1 formed between portions of cover portion 120c that start to concave inwardly) [fig. 3 & para. 64-65 & 89], an isolation opening is formed in the isolation structure (opening in auxiliary electrode 130 corresponding to distance d) [fig. 4 & para. 89], and an orthographic projection of the pixel opening on the array substrate is within an orthographic projection of the isolation opening on the array substrate (orthographic projection of opening op1 overlaps of plurality of pixel-defining layer 120 overlaps with orthographic projection of opening corresponding to auxiliary electrode 130 corresponding to distance d) [fig. 4 & para. 64-65 & 89]; a plurality of first electrodes (plurality of first pixel electrode 211) [figs. 2a-3 & para. 63-66] disposed with intervals; wherein the array substrate comprises a pixel driving circuit (pixel circuits pc) [figs. 2a-3 & para. 41-45 & 61]; the first electrode is connected to the pixel driving circuit in the array substrate (first pixel electrode 211 to pixel circuit pc) [fig. 3]; the pixel defining layer is located on a side, away from the array substrate, of the first electrode, and the pixel opening exposes the first electrode (opening op1) [figs. 3 & 6]; and a light-emitting material layer (first intermediate layer 221 emits light) [fig. 3 & para. 66] and a second electrode (counter electrode 231) [figs. 3-4 & 6 & para. 102] stacked in sequence are disposed in the pixel opening [fig. 3]; and the second electrode extends from the pixel opening to be in electrical contact with the isolation structure (counter electrode 231 directly contact counter electrodes) [figs. 3-4 & 6 & para. 102]. Lee does not explicitly teach the display driver circuit is an integrated circuit, and the isolation structures in a same group are electrically connected to each other, and the isolation structures in different groups are electrically isolated from each other; and a first connection wire disposed in a same layer as the plurality of isolation structures; the display driver integrated circuit is connected to each group of the isolation structures respectively, the display driver integrated circuit is configured to provide independent common voltage for each group of the isolation structures based on a display brightness value command received, the isolation structures in the same group are connected to each other or connected to the display driver integrated circuit through the first connection wire. Im teaches the concept of a display module [abstract] that utilizes a display driver integrated circuit (source drive integrated circuit) [fig. 2 & para. 35, 58, 65, & 67] and a display panel (display panel dp) [figs. 1-3 & para. 35], wherein the display panel comprises: an array substrate (first substrate 110) [figs. 1-2 & para. 36-37]; a plurality of isolation structures (first common power line 310 & second common power line 320) [figs. 3-8 & para. 39-42, 52, & 56] located on a side of the array substrate, wherein the isolation structure is conductive (metal material) [para. 84]; and the plurality of isolation structures are divided into at least two groups (first display area da1 corresponding to first common power line 310 & second display area da2 corresponding to second common power line 320) [figs. 3-8 & para. 68-72, 78-79, 64, 144, 52, & 159], the isolation structures in a same group are electrically connected to each other [figs. 5-6 & para. 68-72, 78-79, 64, 144, 52, & 159], and the isolation structures in different groups are electrically isolated from each other [figs. 5-6 & para. 68-72, 78-79, 64, 144, 52, & 159]; and a first connection wire [figs. 1-2 & 5-6 & para. 68-72, 78-79, 64, 144, 146, 52, & 159] disposed in a same layer as the plurality of isolation structures; the display driver integrated circuit is connected to each group of the isolation structures respectively (source drive integrated circuit) [fig. 2 & para. 35, 58, 65, & 67], the display driver integrated circuit is configured to provide independent common voltage for each group of the isolation structures based on a display brightness value command received (data voltage determines current supplied to oled of pixel during image display. Each grouping of pixels utilizes different common voltage to compensate for voltage drop, the compensation improves uniformity of luminance) [fig. 3 & para. 53-55, 69-72, 76-77, 52, & 47], the isolation structures in the same group are connected to each other or connected to the display driver integrated circuit through the first connection wire [figs. 1-2 & 5-6 & para. 68-72, 78-79, 64, 144, 146, 52, & 159]. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the display driver circuit and the display panel of the display module of Lee, such that the display driver circuit is an integrated circuit, and the isolation structures in a same group are electrically connected to each other, and the isolation structures in different groups are electrically isolated from each other; and a first connection wire disposed in a same layer as the plurality of isolation structures; the display driver integrated circuit is connected to each group of the isolation structures respectively, the display driver integrated circuit is configured to provide independent common voltage for each group of the isolation structures based on a display brightness value command received, the isolation structures in the same group are connected to each other or connected to the display driver integrated circuit through the first connection wire, as taught by Im, to improve image quality by reducing luminance non-uniformity, as taught by Im [para. 84]. Thus, Lee as modified by Im teaches wherein at least two isolation structures of the plurality of isolation structures, respectively corresponding to pixel openings with light-emitting material layers emitting light of different colors (each of intermediate layers 221, 222, 223 correspond to different color) [Lee: para. 59, 76, 91 & Im: para. 146], are located in different groups (first display area da1 & second display area da2) [Im: figs. 5-6 & para. 68-72, 78-79, 64, 144, 146, 52, & 159]. As to claim 4, Lee as modified by Im teaches the display module according to claim 1, wherein the display panel further comprises a first inorganic encapsulation layer (first inorganic film 310 located on side of counter electrodes) [Lee: fig. 18 &para. 146-147] located on a side, away from the array substrate, of the second electrode [Lee: fig. 18 &para. 146-147]. As to claim 5, Lee as modified by Im teaches the display module according to claim 4, wherein at least a part of the first inorganic encapsulation layer extends, along a sidewall of the isolation structure facing the isolation opening, from an inner edge of the pixel opening to a side, away from the array substrate, of the isolation structure (first inorganic film 310) [Lee: fig. 18 &para. 146-147]. As to claim 16, Lee teaches a display module [abstract], comprising a display driver circuit (data driver) [para. 38] and a display panel (organic light-emitting display apparatus 1) [fig. 1 & para. 38], wherein the display panel [figs. 1 & 3 & para. 38 & 60] comprises: an array substrate (substrate 100) [figs. 1 & 3 & para. 60]; and a plurality of pixel units [figs. 1-3 & para. 38-40] located on a side of the array substrate, wherein the plurality of pixel units are divided into at least two groups (each of intermediate layers 221, 222, 223 correspond to different color) [para. 59, 76, 91], the display driver circuit is connected to each group of the pixel units [figs. 1-3 & para. 38-40]; wherein each of the plurality of pixel unit comprises a first electrode (first pixel electrode 211) [figs. 2a-3 & para. 63-66], a light-emitting material layer (first intermediate layer 221 emits light) [fig. 3 & para. 66], and a second electrode (counter electrode 231) [figs. 3-4 & 6 & para. 102] stacked in sequence, the array substrate comprises a pixel driving circuit (pixel circuits pc) [figs. 2a-3 & para. 41-45 & 61], the first electrode is connected to the pixel driving circuit in the array substrate (first pixel electrode 211 to pixel circuit pc) [fig. 3]; light-emitting material layers of the pixel units in a same group have a same light-emitting color (each of intermediate layers 221, 222, 223 correspond to different color, each horizontal row having a same repeating same colors of red green blue) [para. 59, 76, 91], and light-emitting material layers of the pixel units in different groups have different light-emitting colors (each of intermediate layers 221, 222, 223 correspond to different color, each horizontal row having different colors of red green blue) [para. 59, 76, 91]. Lee does not explicitly teach the display driver circuit is an integrated circuit, the display driver integrated circuit is configured to provide independent common voltage for each group of the pixel units based on a display brightness value command received; the second electrode is connected to the display driver integrated circuit; and the second electrodes of a same group of the pixel units are connected to each other through connection wires disposed in a same layer as the plurality of pixel units. Im teaches the concept of a display module [abstract] that utilizes a display driver integrated circuit (source drive integrated circuit) [fig. 2 & para. 35, 58, 65, & 67] and a display panel (display panel dp) [figs. 1-3 & para. 35], wherein the display panel comprises: an array substrate (first substrate 110) [figs. 1-2 & para. 36-37]; and a plurality of pixel units (plurality of unit pixels up) [figs. 1-3 & para. 32] located on a side of the array substrate, wherein the plurality of pixel units are divided into at least two groups (first display area da1 corresponding to first common power line 310 & second display area da2 corresponding to second common power line 320) [figs. 3-8 & para. 68-72, 78-79, 64, 144, 52, & 159], the display driver integrated circuit is connected to each group of the pixel units [para. 32], and the display driver integrated circuit (source drive integrated circuit) [fig. 2 & para. 35, 58, 65, 52, & 67] is configured to provide independent common voltage for each group of the pixel units based on a display brightness value command received (data voltage determines current supplied to oled of pixel during image display. Each grouping of pixels utilizes different common voltage to compensate for voltage drop, the compensation improves uniformity of luminance) [fig. 3 & para. 53-55, 69-72, 76-77, 52, & 47]; and a second electrodes of a same group of the pixel units are connected to each other through connection wires disposed in a same layer as the plurality of pixel units [figs. 1-2 & 5-6 & para. 68-72, 78-79, 64, 144, 146, 52, & 159]. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the display driver circuit and the display panel of the display module of Lee, such that the display driver circuit is an integrated circuit, and the display driver integrated circuit is configured to provide independent common voltage for each group of the pixel units based on a display brightness value command received; and a second electrodes of a same group of the pixel units are connected to each other through connection wires disposed in a same layer as the plurality of pixel units, as taught by Im, to improve image quality by reducing luminance non-uniformity, as taught by Im [para. 84]. Thus, Lee as modified by Im teaches the second electrode is connected to the display driver integrated circuit [Lee: fig. 1 & para. 38 & Im: fig. 2 & para. 35, 58, 65, 52, & 67]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID TUNG whose telephone number is (571)270-3385. The examiner can normally be reached Monday-Friday; 10:00AM - 6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at (571)-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID TUNG/Primary Examiner, Art Unit 2622
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Prosecution Timeline

Nov 15, 2024
Application Filed
Nov 26, 2025
Non-Final Rejection mailed — §103
Feb 14, 2026
Response Filed
Mar 20, 2026
Final Rejection mailed — §103
May 25, 2026
Response after Non-Final Action
Jun 17, 2026
Request for Continued Examination
Jun 19, 2026
Response after Non-Final Action
Jun 24, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
62%
Grant Probability
78%
With Interview (+16.4%)
2y 12m (~1y 3m remaining)
Median Time to Grant
High
PTA Risk
Based on 581 resolved cases by this examiner. Grant probability derived from career allowance rate.

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