Prosecution Insights
Last updated: July 17, 2026
Application No. 18/949,445

MULTILEVEL INVERTER AND ASSOCIATED METHOD

Non-Final OA §102
Filed
Nov 15, 2024
Priority
Dec 05, 2023 — EU 23214190.3
Examiner
MOODY, KYLE J
Art Unit
Tech Center
Assignee
GE Energy Power Conversion Technology Limited
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
505 granted / 558 resolved
+30.5% vs TC avg
Moderate +8% lift
Without
With
+7.9%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
16 currently pending
Career history
571
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
50.1%
+10.1% vs TC avg
§102
24.9%
-15.1% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 558 resolved cases

Office Action

§102
DETAILED ACTION This office action is in response to the application filed on 11/15/24. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Objections Claims 1-15 are objected to because of the following informalities: In regards to claims 1 and 11, it appears that “N=Qn+1-1” should be “N=(Q^(n+1))-1”. In regards to claims 1 and 11, it appears that “the current delivered” should be “a current delivered”. Claims 2-10 an d 12-15 are objected to, based on their dependency of an objected to claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2 and 9-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ye et a. (US20170302195, hereinafter Ye). Regarding Claim 1, Ye discloses a multilevel inverter for converting a direct current (DC) voltage into an alternate current (AC) voltage or an AC voltage into a DC voltage, including at least one phase (fig. 8, 9, 19 implemented with fig. 14), comprising: - a positive input terminal (A1), a negative input terminal (A4), and an output terminal for the at least one phase (A5, A51, A52, A53); - a set of capacitors (C11, (C12+C21), C22) including N capacitors connected in series between both input terminals and connected together through intermediate points (A2, A3), two extreme capacitors of the N capacitors being directly connected to one of the two input terminals, N being an integer so that N=Qn+1-1, Q being an integer equal or greater than two, and n being an integer equal or greater than one; - the inverter having N+1 levels, - a balancing device ( ¶126-130 and inductor when implemented with fig. 14) connected between both input terminals and the intermediate points, and configured to balance the voltage on the terminals of each of the capacitors of the set of capacitors regardless of the DC voltage and the current delivered on the positive and negative input terminals and regardless of the AC voltage and current delivered by the phase, for the output terminal (A5), a switching module (module of Q1-Q6) for switching the DC voltage and being able to convert the DC voltage on the positive and negative input terminals into the AC voltage on the output terminal , or for switching the AC voltage on the output terminal and being able to convert the AC voltage into the DC voltage on the positive and negative input terminals, each switching module comprising: input connections (A1-A4), each input connection being connected to one of the two input terminals or to one of the intermediate points, and supply lines (Q1; Q2-Q4-Q5; Q3-Q4-Q5; Q6), each supply lines connecting an input connection to the output terminal and comprising a plurality of switches connected together in series, characterized in that a set of switches (Q5-Q6) of the plurality of switches of a first supply line (Q2-Q4-Q5) connected to a first input connection (A2) is shared at least with a second supply line (Q3-Q4-Q5) connected to a second input connection (A3) so that a first current flowing from the first input connection to the respective output terminal (A5) and a second current flowing from the second input connection to the respective output terminal flow through the set of switches (Q4-Q5) of the plurality of switches. Regarding Claim 2, Ye discloses (fig. 8, 9, 19)a command circuit configured for switching the switches of each switching module to minimize the voltage at the ends of each switch when the said switch is open (1901, ¶223-231). Regarding Claim 9, Ye discloses (fig. 8, 9, 19) wherein Q is greater or equal than three (fig. 8), N+1 being further the number of input connections and the number of supply lines (fig. 8), switches of the switching module comprising unidirectional switches and bidirectional switches (switches of fig. 8). Regarding Claim 10, Ye discloses (fig. 8, 9, 19 implemented with fig. 14) the balancing device comprises two switching modules and an inductor, each input connection of the two switching modules of the balancing device being connected to one of the two input terminals or to one of the intermediate points, the output terminal of each switching module of the balancing device being connected to an end of the inductor (¶179). Regarding method claim 11, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. Allowable Subject Matter Claims 3-8 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 3, the prior art fails to disclose: “...wherein Q is equal to two, N+1 being further the number of input connections and the number of supply lines, each switching module comprising (N+1)*log(N+1)/log(2) switches, each supply lines comprising N switches..” in combination with the additionally claimed features, as are claimed by the Applicant. Regarding claim 12, the prior art fails to disclose: “...wherein Q is equal to two, N+1 being further the number of input connections and the number of supply lines, each switching module comprising log(N+1)/log(2)*(N+1) switches, each supply lines comprising N switches.” in combination with the additionally claimed features, as are claimed by the Applicant. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 10277144, Soeiro; Thiago-Batista et al. discloses a four-level power converter. US 11831233, Gazit; Meir et al. discloses a multilevel converter circuit and method with discrete voltage levels US 20100328977, Asplund; Gunnar discloses a method for controlling a voltage source converter and a voltage converting apparatus US 20150288284, LAVIEVILLE; Jean-Paul discloses a multi-level power converter. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYLE J MOODY/ Primary Examiner, Art Unit 2838
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Prosecution Timeline

Nov 15, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12683515
POWER CONVERSION DEVICE AND CONTROL METHOD THEREOF
2y 2m to grant Granted Jul 14, 2026
Patent 12683479
SWITCHING POWER SUPPLY CONTROL METHOD AND SWITCHING POWER SUPPLY
2y 2m to grant Granted Jul 14, 2026
Patent 12676542
CIRCUIT FOR GENERATING AUXILIARY POWER
2y 6m to grant Granted Jul 07, 2026
Patent 12671343
A BIDIRECTIONAL DC-DC CONVERTER AND A METHOD OF CONTROLLING SAID BIDIRECTIONAL DC-DC CONVERTER
2y 5m to grant Granted Jun 30, 2026
Patent 12665485
MULTI-VOLTAGE POWER MANAGEMENT INTEGRATED CIRCUIT
2y 0m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+7.9%)
2y 0m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 558 resolved cases by this examiner. Grant probability derived from career allowance rate.

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