DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,833,669 B2).
Regarding Claim 1, Hiyama et al. teaches in Figure 4 an apparatus, comprising:
an SiC FET (Q1, Q2); and
a sense buffer circuit to sense a gate-to-source voltage (VGS) of the SiC FET (using STH, U13, and PCH; using STL, U16, and PCL),
wherein a buffer circuit at an input of the sense buffer circuit has a smaller input voltage range than the sense buffer circuit (where input of STH, STL is based in part on V3; which is higher than the input voltage range of U3, U8 from the low-voltage section).
Regarding Claim 2, Hiyama et al. further teaches the apparatus, wherein the sense buffer circuit includes a voltage control circuit to regulate a VGS signal of the SiC FET to ensure operation of the buffer circuit within the smaller input voltage range (using U12, U13, and PCH; using U15, U16, and PCL).
Regarding Claim 3, Hiyama et al. further teaches the apparatus, wherein the voltage control circuit includes one or more of a voltage scaler, a clamping diode, a voltage attenuator, a floating input, or a signal filter, or respectively to regulate the VGS signal (using V1, PCH; using V2, PCL).
Regarding Claim 4, Hiyama et al. further teaches the apparatus, wherein the buffer circuit to generate a buffered input voltage signal responsive to processing a regulated VGS signal generated by the voltage control circuit (using U1, U6).
Regarding Claim 5, Hiyama et al. further teaches the apparatus, comprising:
a voltage reducer to produce an output signal proportional to a buffered VGS signal and with a scaled amplitude suitable for digital processing within a logic circuit (using U4, U9).
Regarding Claim 6, Hiyama et al. further teaches the apparatus, comprising:
a logic circuit to receive a sensed VGS signal of the SiC FET from the sense buffer circuit, the sensed VGS signal within the operational range of the logic circuit (using U1; using U6).
Regarding Claim 7, Hiyama et al. further teaches the apparatus, comprising:
a driver to provide voltage or current to a gate of the SiC FET suitable to switch the SiC FET between ON and OFF states (using U3; using U8).
Regarding Claim 8, Hiyama et al. further teaches the apparatus, wherein the driver to provide the voltage or current at least partially based on a sensed VGS signal of the SiC FET provided by the sense buffer circuit (using output through U2, U4, U7, and U9).
Regarding Claim 9, Hiyama et al. further teaches the apparatus, wherein the sense buffer circuit further comprises timing control circuitry to synchronize the sampling and buffering of the VGS signal, enabling real-time monitoring of the SiC FET’s gate-to-source voltage (using U12; using U15).
Regarding Claim 10, Hiyama et al. further teaches the apparatus, wherein the sense buffer circuit includes signal conditioning circuitry to modify a VGS signal of the SiC FET (using U13; using U16).
Regarding Claim 11, Hiyama et al. further teaches the apparatus, wherein the signal conditioning circuitry includes one or more of an analog-to-digital converter, a multiplexer, a comparator, a threshold detector, a signal scaler, or a signal level shifter (U13; U16 compares).
Regarding Claim 12, Hiyama et al. further teaches the apparatus, wherein one or more of the inputs of the sense buffer circuit include high-transconductance low-voltage circuits, configured to accurately track changes in the gate-to-source voltage of the SiC FET (from S11, S21).
Regarding Claim 13, Hiyama et al. further teaches the apparatus, wherein the sense buffer circuit includes cascoded low-voltage devices to manage high-voltage swings of the VGS signal while maintaining safe operating conditions for the low-voltage devices (in the low-voltage section of the circuitry).
Allowable Subject Matter
Claim 14 is allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 14, the prior art does not disclose, teach or suggest an apparatus, comprising:
isolation circuitry to electrically isolate the high-voltage VGS input signal from the buffered VGS signal, the isolation circuitry including one or more of cascoded transistors, resistive voltage dividers, clamping diodes, or capacitive coupling;
in combination with all the other claimed limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIANA J. CHENG/Primary Examiner, Art Unit 2849