DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-3, 6-16 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9-13, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shigeru in view of Shinichi [JP 2017/224651A].
As to claim 9. Shigeru discloses A wiring board assembly comprising:
a first electronic component for testing, [fig. 1, 0021] tester 4;
a first wiring board on which the first electronic component is mounted, [fig. 1, 0023] probe card 12 with probes 12a is connected to the tester 4; and
the cooling plate according to claim 1, [figs. 1, 4, 0023] device 10.
Shigeru fails to disclose wherein the first wiring board is disposed on the cooling plate, such that the first electronic component is interposed between the first wiring board and the cooling plate.
Shinichi teaches a cooler comprising a first and second plates 30a and 30b, each comprising grooves 31 forms a fluid path, [fig. 5, 0015]; wherein the transistor chips 21a, 21b to be tested and cooled are sandwiched between the two cooling plates 31a, 31b, [figs. 3, 5, 0018].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Shigeru with that of Shinichi so that device under test can have a maximum surface area exposed to the cooling liquid.
As to claim 10. Shigeru fails to disclose The wiring board assembly according to claim 9, further comprising: a first heat transfer layer that contacts the first electronic component and contacts a first outer surface of the cooling plate.
Shinichi teaches a cooler comprising a first and second plates 30a and 30b, each comprising grooves 31 forms a fluid path, [fig. 5, 0015]; wherein the transistor chips 21a, 21b to be tested and cooled are sandwiched between the two cooling plates 30a, 30b, [figs. 3, 5, 0018]; further comprising a heat sink 17, [fig. 3, 0018].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Shigeru with that of Shinichi so that heat sink can used to contact the heat from the device to be tested to the cooling system.
As to claim 11. Shigeru fails to disclose The wiring board assembly according to claim 9, further comprising: a second electronic component for testing; and a second wiring board on which the second electronic component is mounted, wherein the second wiring board is disposed on the cooling plate such that the second electronic component is interposed between the second wiring board and the cooling plate, and the cooling plate is interposed between the first wiring board and the second wiring board.
Shinichi teaches a cooler comprising a first and second plates 30a and 30b, each comprising grooves 31 forms a fluid path, [fig. 5, 0015]; wherein the transistor chips 21a, 21b to be tested and cooled are sandwiched between the two cooling plates 30a, 30b, [figs. 3, 5, 0018]; wherein each transistor is connected to control terminals 4 in a series connection; wherein the chips and the connections are between the two plates 30a, 30b, [figs. 3, 4].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Shigeru with that of Shinichi so that the system can be used to test a plurality of devices at the same time saving time for testing.
As to claim 12. Shigeru fails to disclose The wiring board assembly according to claim 11, further comprising: a second heat transfer layer that contacts the second electronic component and contacts a second outer surface of the cooling plate.
Shinichi teaches a cooler comprising a first and second plates 30a and 30b, each comprising grooves 31 forms a fluid path, [fig. 5, 0015]; wherein the transistor chips 21a, 21b to be tested and cooled are sandwiched between the two cooling plates 30a, 30b, [figs. 3, 5, 0018]; further comprising a heat sink 17 for each transistor to be tested, [fig. 3, 0018].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Shigeru with that of Shinichi so that heat sink can used to contact the heat from the device to be tested to the cooling system.
As to claim 13. Shigeru discloses A device testing apparatus that tests a device under test (DUT), [fig. 1, 0021], the device testing apparatus comprising: the wiring board assembly according to claim 9, [fig. 1].
As to claim 15. Shigeru fails to disclose The device testing apparatus according to Claim 13, wherein the cooling liquid is water.
Shinichi teaches a cooler comprising a first and second plates 30a and 30b, each comprising grooves 31 forms a fluid path, [fig. 5, 0015]; wherein the refrigerant is water, [0009].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of Shigeru with that of Shinichi so that the cooling system can be implemented using a readily available resource.
As to claim 16. Shigeru discloses The device testing apparatus according to Claim 13, further comprising: a test head that accommodates the wiring board assembly comprising a pin electronics card, [fig. 1, 0023] probes 12a is connected to the tester 4, wherein the pin electronics card comprises: the first wiring board, [fig. 1, 0023] probe card 12 ; and the first electronic component, [fig. 1, 0021] tester 4.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shigeru in view of Shinichi as applied to claim 13 above, further in view of Ward et al. [US 20130092356].
As to claim 14. Shigeru discloses The device testing apparatus according to claim 13, further comprising: a cooling liquid supply device that supplies a cooling liquid to the flow path in the cooling plate, [fig. 1, 4] a refrigerant supply pipe 160 supplying the refrigerant, which requires a refrigerant supply device to supply the refrigerant.
The combination of Shigeru and Shinichi fails to disclose wherein the apparatus further comprises an ion removing filter that is interposed between the cooling liquid supply device and the wiring board assembly and removes ions from the cooling liquid.
Ward teaches a system for testing a device under test DUT using a cooling fluid, [fig. 4, 0044], wherein the system comprises a particle filter 10 inline with the fluid path 32, [fig. 4, 0044], to remove charged particles from the fluid, [0035].
It would have been obvious for one of ordinary skill in the art at the time of the filing of the claimed invention to combine the teachings of the combination of Shigeru and Shinichi with that of Ward so that the cooling fluid can be free of impurities and perform at a higher efficiency.
Allowable Subject Matter
Claims 1-3, 6-8 are allowed.
Response to Arguments
Applicant's arguments filed 09/22/2026 have been fully considered but they are not persuasive.
Argument 1: as to claims 9, 13, the grooves 31, as cited in Shinichi, include no recess that accommodates the resin as the adhesive part along one side and another side of the grooves 31.
Response 1: In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “recess that accommodates the resin as the adhesive part”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENYAM HAILE whose telephone number is (571)272-2080. The examiner can normally be reached 7:00 AM - 5:30 PM Mon. - Thur..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Lim can be reached at (571)270-1210. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Benyam Haile/Primary Examiner, Art Unit 2688
