MEMORY DEVICE

Application No. 18/949,858

• Filed: Nov 15, 2024
• Priority: Feb 01, 2021 — CN 202110136033.9
  • Feb 23, 2021 — continuation of 11/393,509
  • Jun 29, 2022 — continuation of 11/721,374
  • Jun 16, 2023 — continuation of 12/176,062
• Examiner: YANG, HAN
• Assignee: Tsmc China Company Limited
• OA Round: 1 (Non-Final)

Office Action

Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

2. Claim(s) 1-6, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Barth, JR. et al (Pub. No.: US 2020/0051658).
3. Regarding independent claim 1, Barth, JR. et al teaches a memory device (Fig. 1), comprising: a first logic element (Fig. 1, #44) configured to generate a first global write signal (Fig. 1, D_T) based on a clock signal (Fig. 1, CLK) and a first latch write data (Fig. 1, the output of #50 into #44); a second logic element (Fig. 1, #46) configured to generate a second global write signal (Fig. 1, D_C) based on the clock signal (Fig. 1, CLK) and a second latch write data (Fig. 1, output of #48); and a third logic element (Fig. 1, #48) configured to receive the first latch write data (Fig. 1, the output of #50 into #44) to output the second latch write data (Fig. 1, output of #48).
4. Regarding claim 2, Barth, JR. et al teaches a first latch (Fig. 1, latch 50) configured to generate the first latch write data (Fig. 1, the output of #50 into #44) according to the clock signal (Fig. 1, CLK).
5. Regarding claim 3, Barth, JR. et al teaches the first latch configured to receive a write data (Fig. 1, D) and be triggered by the clock signal (Fig. 1, CLK) to generate the first latch write data (Fig. 1, the output of #50 into #44).
6. Regarding claim 4, Barth, JR. et al teaches a second latch (Fig. 1, latch 54) configured to be triggered by the clock signal (Fig. 1, CLK); and a fourth logic element (Fig. 1, #56) coupled to an output terminal of the second latch (Fig. 1, #54), and configured to output a write mask signal (Fig. 1, Q) to each of the first logic element (Fig. 1, #44) and the second logic element (Fig. 1, #46).
7. Regarding claim 5, Barth, JR. et al teaches a logic type of the third logic element (Fig. 1, #48) is same as a logic type of the fourth logic element.
8. Regarding claim 6, Barth, JR. et al teaches a logic type of the first logic element (Fig. 1, #44) is same (see Fig. 1) as a logic type of the second logic element (Fig. 1, #46).

Allowable Subject Matter

9. Claims 7-20 are allowed.
10. With respect to claim 7, there is no teaching, suggestion, or motivation for combination in the prior art to a first switch configured to provide a reference voltage signal to the first logic element according to a write enable signal; a second switch configured to provide the reference voltage signal to the second logic element according to the write enable signal; a third switch configured to transmit the first local write signal according to a first selection signal; and a fourth switch configured to transmit the second local write signal according to the first selection signal.

11. With respect to dependent claims 8-14, since these claims are depending on claim 7, therefore claims 8-14 are allowable subject matter.
12. With respect to claim 15, there is no teaching, suggestion, or motivation for combination in the prior art to pulling the selection signal by a third switch and a fourth switch coupled in series with each other; controlling the first switch by the first local write signal; and controlling the second switch by the second local write signal.

13. With respect to dependent claims 16-20, since these claims are depending on claim 15, therefore claims 16-20 are allowable subject matter.

Conclusion

14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, YAMAGAMI (Pub. No: US 20201/0005838), Lee (Pub. No.: US 2015/0121097).
YAMAGAMI (Pub. No: US 20201/0005838) shows write data signals.
Lee (Pub. No.: US 2015/0121097) shows global writing signals
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is [phone]. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].
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HY
06/23/2026
/HAN YANG/
Primary Examiner, Art Unit 2824

Prosecution Timeline

• Nov 15, 2024: Application Filed
• Jun 26, 2026: Non-Final Rejection mailed — §102 (current)