DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the response to amendment filed 8/20/2026. Claims 1-15 and 20-23 are under examination. Claims 16-19 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8 and 20-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dash (USP 7,110,729).
Regarding claim 1, Dash’s figure 2 shows A circuit within an integrated circuit package comprising: an amplifier (230, 240) having an amplifier output (node where Ml(x) and Nl(y) summed up) including a proportional to absolute temperature (PTAT 210) and a complementary to absolute temperature (CTAT) (220) circuit coupled to the amplifier output , the amplifier configurable to set a state of the amplifier output responsive to the comparison between a first current (l(x)) provided by the PTAT circuit and a second current (l(y)) provided by the CTAT circuit ; and a heating element (250 is a transistor that capable of being heated) disposed within the integrated circuit package and having a control terminal coupled to the amplifier output as called for in claim 1.
Regarding claim 2, wherein the heating element is a transistor (250).
Regarding claim 3, the heating element is an n-type metal oxide field effect transistor (nMOSFET).
Regarding claim 6, wherein the CTAT current source includes a current mirror that has three transistors with control terminals coupled to each other (410, 420, 240).
Regarding claim 7, wherein the PTAT current sink includes a current mirror that has three transistors with control terminals coupled to each other (310, 320, 230).
Regarding claim 8, wherein the circuit a reference circuit (125).
Regarding claim 20, Dash’s figures 1-2 shows A circuit comprising a circuit in a package having an output at a predetermined temperature (controller provides an output at a predetermined temperature); a variable heater (250) disposed in the package and having a control terminal; an amplifier (230, 240) having an amplifier output (node where Ml(x) and Nl(y) summed up) including a proportional to absolute temperature (PTAT 210) and a complementary to absolute temperature (CTAT) (220) circuit coupled to the amplifier output , the amplifier configurable to set a state of the amplifier output responsive to the comparison between a first current (l(x)) provided by the PTAT circuit and a second current (l(y)) provided by the CTAT circuit ; and a heating element (250 is a transistor that capable of being heated) disposed within the integrated circuit package and having a control terminal coupled to the amplifier output; wherein the first current equals to the second current at the predetermined temperature (output current (Iout) is constant at predetermined temperature) as called for in claim 20.
Regarding claim 21, the differential absolute-temperature comparator comprises a first current source (310, 320) and a second current source (410, 420).
Regarding claim 22, wherein the temperature-dependent circuit and controller (125) is capable of being a clock generation circuit.
Regarding claim 23, wherein the heating element (250) is configured to modulate a temperature of the circuit to a selected temperature (output current (Iout) is constant at predetermined temperature).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dash (USp 7,110,729) in view of Hornung et all. (US 2015/0187760).
Regarding claim 4, Dash reference discloses a circuit comprising all the aspects of the present invention as noted above with the CTAT (220) comprising a current mirror (410, 420) coupled to MOS transistors (430, 440) instead of being bipolar junction transistor as called for in claim 4. However, it is notoriously well known in the art that bipolar transistors offer better speed than MOS transistors (see Hornung et al.’s paragraph 0003). Therefore, it would have been obvious to person skilled in the art before effective filing date of the invention to have Dash’s MOS transistors be replaced with bipolar transistors for the purpose of increasing operational speed as taught by Hornung et al. reference.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dash (USp 7,110,729) in view of Willemin et al. (US 2016/0172898).
Regarding claim 5, Dash reference discloses a circuit comprising all the aspects of the present invention as noted above with the PTAT current sink (210) includes a first current mirror having transistors of a first polarity ( 310, 320; P type transistors). Dash further discloses a second current mirror (330, 340) in NPN bipolar transistors with a second polarity (NPN) instead of MOS transistors being N type transistors as called for in claim 5. However, it is notoriously well known in the art that N type transistors are preferable because of its low power consumption (see Willemin et al.’s paragraph 0067). Therefore, it would have been obvious to person skilled in the art before effective filing date of the invention to have Dash’s NPN transistors be replaced with N type transistors for the purpose of reducing power consumption as taught by Willemin et al. reference.
Allowable Subject Matter
Claims 9-15 are presently allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to teach or fairly suggest a first transistor disposed within the substrate and having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the output terminal of the first current mirror, and the control terminal of the first transistor coupled to the reference terminal of the first current mirror, the first transistor having a second polarity; a second transistor disposed within the substrate and having a first terminal and a control terminal, the control terminal of the second transistor coupled to the second terminal of the first transistor, the first terminal of the second transistor coupled to the reference terminal of the first current mirror; a differential amplifier disposed within the substrate and having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the differential amplifier coupled to reference terminal of the first current mirror; and a third current mirror disposed within the substrate and having a reference terminal and an output terminal, the reference terminal of the third current mirror coupled to the output terminal of the second current mirror, and the output terminal of the third current mirror coupled to the reference terminal of the second current mirror; and a third transistor having a control terminal coupled to the output terminal of the differential amplifier as called for in claim 9. Therefore, claims 9-15 are presently allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 9/28/2026
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