DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Status
This office action is responsive to the Application No.:18/950,776 filed on 11/18/2024.
Claims 1-20 are pending and presented for examination.
This action has been made NON-FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/18/2024 is being considered by the examiner. A signed IDS is hereby attached.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-7, 9, 11-14, 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Peng, US 20170098328 in view of Toksvig, US 20100259536.
Claim 1:
Peng discloses an apparatus (See Peng Abstract). Peng failed to disclose return sequence. Toksvig discloses this feature in paragraph 0064. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Peng by the teachings of Toksvig to enable improved processing on graphics by incorporating return sequence, more effectively (See Toksvig Field of Invention). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as, image/graphic processing. This close relation between both references highly suggests an expectation of success.
As modified:
The combination of Peng and Toksvig discloses the following:
shader processor circuitry configured to execute instructions of shader programs (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053);
texture storage circuitry configured to store surface data (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053);
and texture processor circuitry configured to access the texture storage circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053);
wherein: the shader processor circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053) is configured to execute a multi-fetch instruction that specifies (See Peng Paragraphs 0003-0004):
an access location and shape information for a thread (See Peng Paragraphs 0003-0004; 0037-0038);
and return sequence information that indicates an ordering of return data (See Toksvig Paragraph 0064) for the multi-fetch instruction (See Peng Paragraphs 0003-0004);
and the texture processor circuitry is configured to (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053), based on the multi-fetch instruction (See Peng Paragraphs 0003-0004) and the shape information (See Peng Paragraphs 0037-0038):
access multiple texels of a surface stored by the texture storage circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053), wherein a plurality of the multiple texels are accessed at least partially in parallel (See Peng Paragraphs 0033-0034);
and provide the accessed multiple texels to the shader processor circuitry for the thread, over multiple clock cycles (See Peng Paragraph 0044), according to the ordering specified by the return sequence information (See Toksvig Paragraph 0064).
Claim 2:
The combination of Peng and Toksvig discloses wherein: the texture processing circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053) includes: a first filter pipeline that includes a first set of multiple sample lanes (See Peng Paragraphs 0004; 0031-0034); and a second filter pipeline that includes a second set of multiple sample lanes (See Peng Paragraphs 0004; 0031-0034); and control circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053) configured to map the accesses to the multiple texels of the surface to multiple samples lanes of the first set of multiple sample lanes (See Peng Paragraphs 0004; 0031-0034) and to multiple sample lanes of the second set of multiple sample lanes (See Peng Paragraphs 0004; 0031-0034).
Claim 4:
The combination of Peng and Toksvig discloses wherein the shape information indicates a width and a height (See Peng Paragraphs 0003-0004; 0031-0034; 0037) in texture space (See Peng Paragraphs 0003-0004; 0031-0034).
Claim 5:
The combination of Peng and Toksvig discloses wherein the texture processor circuitry is configured to access the multiple texels from the texture storage circuitry in a single clock cycle (See Peng Paragraph 0044).
Claim 6:
The combination of Peng and Toksvig discloses wherein the texture processor circuitry is configured to store the multiple accessed texels in multiple general-purpose registers of the shader processor circuitry (See Peng Paragraphs 0029; 0074).
Claim 7:
The combination of Peng and Toksvig discloses wherein the access location (See Peng Paragraph 0003) is specified as an integer (See Peng Paragraph 0032) coordinate in a texture space (See Peng Paragraphs 0003-0004; 0031-0034).
Claim 9:
The combination of Peng and Toksvig discloses wherein the shape information is encoded to specify a shape, relative to the access location in texture space, wherein the encoding supports two or more of the following shapes: 1x2 texels, 2x1 texels, 1x4 texels, 4x1 texels, and 2x2 texels (See Peng Paragraph 0033).
Claim 11:
The combination of Peng and Toksvig discloses wherein the texture storage circuitry is a texture cache with entries that are tagged based on locations in texture space (See Peng Paragraph 0003).
Claim 12:
The combination of Peng and Toksvig discloses wherein the apparatus is a computing device that further includes: a central processing unit (See Peng Paragraph 0054); a display (See Peng Paragraph 0057); and network interface circuitry (See Peng Paragraphs 0056-0062; 0051).
Claim 13:
Claim 13 is rejected on the same basis as claim 1.
Claim 14:
Claim 14 is rejected on the same basis as claim 2.
Claims 16 and 17:
Claims 16 and 17 are rejected on the same basis as claims 4 and 5.
Claim 19:
Claim 19 is rejected on the same basis as claim 1.
Claim(s) 3, 10, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Peng, US 20170098328 in view of Toksvig, US 20100259536 and in further view of Keller, US 20220129755.
Claim 3:
The combination of Peng and Toksvig failed to disclose sparsity mask however Keller discloses this feature in paragraph 0131. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Peng and Toksvig by the teachings of Keller to enable improved processing of images and recognition by incorporating sparsity mask, more effectively (See Keller Paragraph 0003). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as, image processing. This close relation between both references highly suggests an expectation of success.
As modified:
The combination of Peng, Toksvig and Keller disclose the following:
the multi-fetch instruction (See Peng Paragraphs 0003-0004) further specifies sparsity mask information (See Keller Paragraph 0131) that indicates a subset of texels within a shape specified by the shape information (See Peng Paragraphs 0004; 0037-0039; 0041); and the multiple texels accessed (See Peng Paragraphs 0003-0004) and provided by the texture processor circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053) include only the subset of texels and does not include one or more other texels within the shape (See Peng Paragraphs 0004; 0037-0039; 0041).
Claim 10:
The combination of Peng and Toksvig failed to disclose a single-instruction multiple-thread (SIMT) however Keller discloses this feature in paragraph 0059. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Peng and Toksvig by the teachings of Keller to enable improved processing of images and recognition by incorporating SIMT, more effectively (See Keller Paragraph 0003). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as, image processing. This close relation between both references highly suggests an expectation of success.
As modified:
The combination of Peng, Toksvig and Keller disclose the following:
wherein the multi-fetch instruction (See Peng Paragraphs 0003-0004) is a single-instruction multiple-thread (SIMT) sample instruction (See Keller Paragraph 0059) and the texture processor circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053) is configured to access multiple texels of the texture (See Peng Paragraphs 0003-0004) for a first SIMT thread and multiple texels of the texture for a second SIMT thread (See Keller Paragraph 0059).
Claims 15 and 20:
Claims 15 and 20 are rejected on the same basis as claim 3.
Claim(s) 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Peng, US 20170098328 in view of Toksvig, US 20100259536 and in further view of FIELDING, US 20220215613.
Claim 8:
The combination of Peng and Toksvig failed to disclose disable the filter. However, FIELDING discloses this feature in paragraph 0447. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Peng and Toksvig by the teachings of FIELDING to enable improved render an output in a graphics processing system by incorporating the disablement of filters, more effectively (See FIELDING Abstract). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as, graphics texture. This close relation between both references highly suggests an expectation of success.
As modified:
The combination of Peng, Toksvig and FIELDING disclose the following:
wherein: the texture processor circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053) includes filter circuitry configured to perform filter operations on multiple accessed texels (See Peng Paragraphs 0031-0033); and the texture processor circuitry (See Peng Figure 7; Paragraphs 0031-0033; 0051-0053) is configured to disable the filter circuitry (See FIELDING Paragraph 0447) for the multi-fetch instruction (See Peng Paragraphs 0003-0004) and provide the multiple texels without filtering (See FIELDING Paragraph 0447).
Claim 18:
Claim 18 is rejected on the same basis as claim 8.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hillesland, US20170178397 discloses a graphics processing unit is configured to map pixels of a first frame of a video stream to texels, select a subset of the texels for shading based on previously cached texels that were shaded for a second frame, and shade the subset of the texels. The graphics processing unit is also configured to cache the shaded subset of the texels with the previously cached texels and determine values for the pixels of the first frame based on the cached texels.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEREE N BROWN whose telephone number is (571)272-4229. The examiner can normally be reached M-F 5:30-2:00 PM EST.
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/SHEREE N BROWN/Primary Examiner, Art Unit 2612 June 16, 2026
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