DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 13 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Verma et al. 10990517 herein Verma in view of Sato 20030158966 herein Sato.
Per claim 1, Verma discloses: a memory sub-system controller comprising a plurality of controller channels, wherein the memory sub-system controller provides a plurality of channel mappings, (fig. 2 & 3c,; col. 6; The programmable device 320 may use a subset of the bits for each address to interleave the requests from the host 310 across multiple communication channels and HBMs, e.g., A0, A1, . . . , A7….. It is appreciated that in some examples, the programmable device 320 is configured to remap the address associated with each read/write request, e.g., in[i], of the plurality of read/write requests to a physical address, e.g., a.sub.31, a.sub.30, a.sub.29, . . . , a.sub.0, in the memory through appropriate communication channel, e.g., A0, A1, . . . , A7, using an offset;) wherein the one or more memory devices comprise a plurality of memory dies, wherein each memory channel of the plurality of memory channels corresponds to a respective one of the plurality of memory dies; (col. 10; The interleaver round-robin scheduler 620 is configured to interleave the received requests stored in DDR 610, as described above with respect to FIGS. 1A-5. The interleaved requests are transmitted to a set of processing units (Pus) 630 such that the requests in the interleaved fashion are transmitted via their appropriate communication channels, e.g., DDR 642, 644, . . . , 646, to the memory) and a channel switch circuit coupled between the plurality of the controller channels and the plurality of memory channels, (fig. 2 & 3c, col. 7 line56;) wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing (fig. 2 & 3c, col. 7 line 56; the processing units 323 process the write request from the host 310 and use a subset of the address associated with the request, [a.sub.2, a.sub.1, a.sub.0], to determine the appropriate communication channel. Once the appropriate channel is determined, the switch 322 in the programmable device 320 is manipulated to route the write request to the appropriate HBM 330).
Verma does not specifically disclose: determines a plurality of channel mappings based on usage of the plurality of controller channels and a plurality of memory channels; wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing, and wherein the channel switch circuit receives the plurality of channel mappings from the memory sub-system controller and performs the data routing according to the plurality of channel mappings.
However, Sato discloses: determines a plurality of channel mappings based on usage of the plurality of controller channels and a plurality of memory channels; (fig. 2, ¶0053; when a plurality of storage subsystems 102 belong to the target storage management group 10, the fiber channel switch 101 selects a route to a storage control device lowest in access frequency from the storage control master device 12 and storage control replica devices 13, and relays the access request to the selected storage subsystem 102.) wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing, and wherein the channel switch circuit receives the plurality of channel mappings from the memory sub-system controller and performs the data routing according to the plurality of channel mappings (¶0059; A fiber channel switch collects information from the storage control master device and the storage control replica devices, and has route mapping information. When a server is started in such an environment, the server, first, requests access in accordance with the stored storage management group information possessed by the server. On this occasion, the fiber channel switch validates only an access route to a storage control device lowest in access frequency, selected from the storage control master and replica devices on the basis of the storage management group information possessed by the server and the route mapping information possessed by the switch itself. In this example, the fiber channel switch decides that the replica device 2 is lowest in access frequency, and the fiber channel switch validates only the route to the replica device 2).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the memory routing of Verma, Sato because Sato to acquire storage management information to control the storage server. Sato improves the storage efficiency (¶0008).
Claim 13 is the circuit claim corresponding to the system claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1.
Claim 17 is the device claim corresponding to the system claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1.
Claim(s) 2-12, 14-16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Verma et al. 10990517 herein Verma and Sato in view of Himelstein et al herein Himelstein.
Per claim 2, Verma discloses: wherein a first channel mapping of the plurality of channel mappings identifies a first controller channel of the plurality of controller channels and one or more first memory channels of a plurality of memory channels, and wherein a second channel mapping of the plurality of channel mappings identifies a second controller channel of the plurality of controller channels and one or more second memory channels of the plurality of memory channels (fig. 2 & 3c,; col. 6; The programmable device 320 may use a subset of the bits for each address to interleave the requests from the host 310 across multiple communication channels and HBMs, e.g., A0, A1, . . . , A7….. It is appreciated that in some examples, the programmable device 320 is configured to remap the address associated with each read/write request, e.g., in[i], of the plurality of read/write requests to a physical address, e.g., a.sub.31, a.sub.30, a.sub.29, . . . , a.sub.0, in the memory through appropriate communication channel, e.g., A0, A1, . . . , A7, using an offset).
The combined teachings of Verma and Sato discloses interleaving requests over a plurality of controller channels but does not specifically disclose: wherein the channel switch circuit comprises command processing logic configured to: route, concurrently, data from the first controller channel of the plurality of controller channels to the one or more first memory channels of the plurality of memory channels that are associated with the first controller channel by the first channel mapping of the plurality of channel mappings, and data from the second controller channel of the plurality of controller channels to the one or more second memory channels of the plurality of memory channels that are associated with the second controller channel by the second channel mapping of the plurality of channel mappings.
However, Himelstein discloses: wherein the channel switch circuit comprises command processing logic configured to: route, concurrently, data from the first controller channel of the plurality of controller channels to the one or more first memory channels of the plurality of memory channels that are associated with the first controller channel by the first channel mapping of the plurality of channel mappings, and data from the second controller channel of the plurality of controller channels to the one or more second memory channels of the plurality of memory channels that are associated with the second controller channel by the second channel mapping of the plurality of channel mappings (col. 12 line 32; a Non-Blocking Parallel Solid State Interface (NBPSI) as described in detail below. These operations may be distributed across many chips and subdivided into local processing steps, as shown in FIG. 8. Referring now to FIG. 8, branch interface controller 202 includes a set of memory interfaces 207 coupled to one or more memory interface controllers 200 and a set of non-blocking parallel solid state interfaces 208 to be coupled to an array of memory leaves. The non-blocking parallel solid state interfaces 208 allow a large amount of IO requests to access the memory leaves in parallel, without blocking each other).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the memory routing of Verma, Sato and Himelstein because Himelstein allows multi threaded applications to achieve parallelism. Himelstein improves the efficiency of data access (col. 4 line 38; The multi-rooted interconnection provides efficient parallel access to the data, thereby enabling concurrent, parallel, and multi-threaded application programs to operate efficiently. As stated previously, specialized system software manages the efficient scheduling of the computation and data access).
Per claim 3, Hinelstein discloses: wherein the command processing logic is further configured to: receive, on a particular one of the plurality of controller channels, a memory access request from the memory sub-system controller; and transfer data between the particular one of the plurality of controller channels and a particular one of the plurality of memory channels in accordance with the memory access request, wherein the particular one of the plurality of memory channels is identified by a channel mapping of the plurality of channel mappings that also identifies the particular one of the plurality of controller channels (fig. 3Acol. 12 line 32; a Non-Blocking Parallel Solid State Interface (NBPSI) as described in detail below. These operations may be distributed across many chips and subdivided into local processing steps, as shown in FIG. 8. Referring now to FIG. 8, branch interface controller 202 includes a set of memory interfaces 207 coupled to one or more memory interface controllers 200 and a set of non-blocking parallel solid state interfaces 208 to be coupled to an array of memory leaves. The non-blocking parallel solid state interfaces 208 allow a large amount of IO requests to access the memory leaves in parallel, without blocking each other).
Per claim 4, Verma discloses: wherein the memory access request comprises a memory address, and the command processing logic is further configured to: determine a memory die corresponding to the memory address, wherein data is transferred between the particular one of the plurality of controller channels and the determined memory die via the particular one of the plurality of memory channels (col. 7-col.8; Once the appropriate channel is determined, the switch 322 in the programmable device 320 is manipulated to route the write request to the appropriate HBM 330. For example, based on [a.sub.2, a.sub.1, a.sub.0] of [1 0 1] it may be determined that the write request is to write to A5 HBM 330. Accordingly, the switch 322 routes the address 324 in[i]=a.sub.31, a.sub.30, a.sub.29, . . . , a.sub.0 associated with a memory location for the write request, to A5 of HBM 330 along with the data to be stored; Once a subset of the address, e.g., 3 least significant bits in this example, is used to determine the HBM channel, the address may be routed via the switch 322. For example, the 3 least significant bits [a.sub.2, a.sub.1, a.sub.0] of [0 1 1] for a read request may be used to identify A7 as the appropriate communication channel of the HBM 330. In another example, the 3 least significant bits [a.sub.2, a.sub.1, a.sub.0] of [0 0 1] for a read request may be used to identify A1 as the appropriate communication channel of the HBM 330. The address 324 in[i]=a.sub.31, a.sub.30, a.sub.29, . . . , a.sub.0 associated with a memory location for the read request may thus be transmitted through the appropriate communication channel to access the appropriate location of the HBM 330, e.g., A7, A1, etc).
Per claim 5, Verma discloses: wherein at least one of the plurality of channel mappings is specified by the memory access request from the memory sub-system controller (col. 7-col.8; Once the appropriate channel is determined, the switch 322 in the programmable device 320 is manipulated to route the write request to the appropriate HBM 330. For example, based on [a.sub.2, a.sub.1, a.sub.0] of [1 0 1] it may be determined that the write request is to write to A5 HBM 330. Accordingly, the switch 322 routes the address 324 in[i]=a.sub.31, a.sub.30, a.sub.29, . . . , a.sub.0 associated with a memory location for the write request, to A5 of HBM 330 along with the data to be stored; Once a subset of the address, e.g., 3 least significant bits in this example, is used to determine the HBM channel, the address may be routed via the switch 322. For example, the 3 least significant bits [a.sub.2, a.sub.1, a.sub.0] of [0 1 1] for a read request may be used to identify A7 as the appropriate communication channel of the HBM 330.).
Per claim 6, Himelstein discloses: wherein at least one of the plurality of channel mappings is specified by a control command received from the memory sub-system controller via at least one of the plurality of controller channels, (fig. 3A, col. 12 line 32; a Non-Blocking Parallel Solid State Interface (NBPSI) as described in detail below. These operations may be distributed across many chips and subdivided into local processing steps, as shown in FIG. 8. Referring now to FIG. 8, branch interface controller 202 includes a set of memory interfaces 207 coupled to one or more memory interface controllers 200 and a set of non-blocking parallel solid state interfaces 208 to be coupled to an array of memory leaves. The non-blocking parallel solid state interfaces 208 allow a large amount of IO requests to access the memory leaves in parallel, without blocking each other).
Himelstein does not specifically disclose: and wherein the control command comprises a controller channel identifier that specifies a particular one of the plurality of controller channels and a memory channel identifier that specifies the particular one of the plurality of memory channels.
However, Verma discloses: and wherein the control command comprises a controller channel identifier that specifies a particular one of the plurality of controller channels and a memory channel identifier that specifies the particular one of the plurality of memory channels (fig. 3A & 21, col. 12 line 32; a Non-Blocking Parallel Solid State Interface (NBPSI) as described in detail below. These operations may be distributed across many chips and subdivided into local processing steps, as shown in FIG. 8. Referring now to FIG. 8, branch interface controller 202 includes a set of memory interfaces 207 coupled to one or more memory interface controllers 200 and a set of non-blocking parallel solid state interfaces 208 to be coupled to an array of memory leaves. The non-blocking parallel solid state interfaces 208 allow a large amount of IO requests to access the memory leaves in parallel, without blocking each other).
Per claim 7, Verma discloses: wherein the command processing logic is further configured to: receive, on each of the plurality of controller channels, a respective memory access request from the memory sub-system controller; and transfer, concurrently, data on each controller channel of the plurality of the controller channels to a respective one of the plurality of memory channels in accordance with the respective memory access request, wherein the respective one of the plurality of memory channels is identified by a channel mapping of the plurality of channel mappings that also identifies the controller channel (col. 7-col.8; Once the appropriate channel is determined, the switch 322 in the programmable device 320 is manipulated to route the write request to the appropriate HBM 330. For example, based on [a.sub.2, a.sub.1, a.sub.0] of [1 0 1] it may be determined that the write request is to write to A5 HBM 330. Accordingly, the switch 322 routes the address 324 in[i]=a.sub.31, a.sub.30, a.sub.29, . . . , a.sub.0 associated with a memory location for the write request, to A5 of HBM 330 along with the data to be stored; Once a subset of the address, e.g., 3 least significant bits in this example, is used to determine the HBM channel, the address may be routed via the switch 322. For example, the 3 least significant bits [a.sub.2, a.sub.1, a.sub.0] of [0 1 1] for a read request may be used to identify A7 as the appropriate communication channel of the HBM 330. In another example, the 3 least significant bits [a.sub.2, a.sub.1, a.sub.0] of [0 0 1] for a read request may be used to identify A1 as the appropriate communication channel of the HBM 330. The address 324 in[i]=a.sub.31, a.sub.30, a.sub.29, . . . , a.sub.0 associated with a memory location for the read request may thus be transmitted through the appropriate communication channel to access the appropriate location of the HBM 330, e.g., A7, A1, etc).
Per claim 8, Himelstein discloses: wherein each respective one of the plurality of memory channels to which the data is transferred is in a same memory device of the one or more memory devices (fig. 21).
Per claim 9, Himelstein discloses: wherein the channel switch circuit comprises: a plurality of controller channel Input/Output (I/O) circuits, wherein each of the plurality of controller channel I/O circuits is coupled to a respective one of the plurality of controller channels, and a plurality of memory channel I/O circuits, wherein each of the plurality of memory channel I/O circuits is coupled to a respective one of the plurality of memory channels (fig. 21).
Per claim 10, Himelstein discloses: wherein the channel switch circuit comprises one or more pins associated with a channel mapping control signal, and at least one of the plurality of channel mappings is specified by the channel mapping control signal (fig.21, col. 7 line 43; when processor core 121A attempts to access data stored in memory leaves 114B, it places a command in SW 123A. Branch 112A then executes the command from SQ 123A. Branch 112A communicates with branch 112B via memory fabric 116 based on the command to request the operation to be performed at root 108B. In response branch 112B performs the requested operation. Once the operation has been completed, branch 112B communicates the result of the operation back to branch 112A. Branch 112A places the result in CQ 124A, which in turn will notify memory controller 110A and processor core 121A. Branches 112 and 112B may communicate with each other using a variety of signaling protocols or communication protocols (e.g., Ethernet protocols). Since there is one set of SQ and CQ for each of the processor cores, the above operations can be performed in parallel for multiple processor cores executing multiple threads).
Per claim 11, Himelstein discloses: wherein the command processing logic is further configured to: determine one or more logical levels, wherein each logical level of the one or more logical levels is determined from one of the one or more pins; and determine the at least one of the plurality of channel mappings based on the one or more logical levels (fig.21, col. 7 line 43; when processor core 121A attempts to access data stored in memory leaves 114B, it places a command in SW 123A. Branch 112A then executes the command from SQ 123A. Branch 112A communicates with branch 112B via memory fabric 116 based on the command to request the operation to be performed at root 108B. In response branch 112B performs the requested operation. Once the operation has been completed, branch 112B communicates the result of the operation back to branch 112A. Branch 112A places the result in CQ 124A, which in turn will notify memory controller 110A and processor core 121A. Branches 112 and 112B may communicate with each other using a variety of signaling protocols or communication protocols (e.g., Ethernet protocols). Since there is one set of SQ and CQ for each of the processor cores, the above operations can be performed in parallel for multiple processor cores executing multiple threads).
Per claim 12, Himelstein discloses: wherein the one or more logical levels are determined during a period of time in which a write request or a read request is received via at least one of the plurality of controller channels (fig.21, col. 7 line 43; Branches 112 and 112B may communicate with each other using a variety of signaling protocols or communication protocols (e.g., Ethernet protocols). Since there is one set of SQ and CQ for each of the processor cores, the above operations can be performed in parallel for multiple processor cores executing multiple threads).
Claims 14-16 are the circuit claims corresponding to the system claims 2-12 and are rejected under the same reasons set forth in connection with the rejection of claims 2-12.
Claims 18-20 are the device claims corresponding to the system claims 2-12 and are rejected under the same reasons set forth in connection with the rejection of claims 2-12.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Prosecution Insights