DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species II in the reply filed on July 01, 2026, is acknowledged. The traversal is on the ground(s) that the species distinctions are based upon structural differences in the figures and not based upon the claim language. Species I concerns coordinated detection across power multiple domains, where Species II relies on a single power domain implementation involving a retention-voltage level and retention-time limitation. This is not found persuasive because according to MPEP a requirement for election of species is proper when claims are directed to different species that fall within the scope of a generic claim. (see MPEP $806.04).
The requirement is still deemed proper and is therefore made FINAL.
Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on July 01, 2026.
Status of Claims
The following is a Non-Final Office Action in response to applicant’s filing on July 01, 2026. Claims 10-20 are withdrawn from consideration. Claims 1-9 are examined in this action. Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/18/2024 and 04/04/2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract is objected to because it is presented in more than one paragraph. The abstract must be a single paragraph pursuant to 37 CFR 1.72(b). applicant is required to amend the abstract so that the entire abstract appears as a single paragraph.
The disclosure is objected to because of the following informalities:
In paragraph [0018], “an attackers probe point 28” should be changed to “an attacker’s probe point 28”.
In paragraph [0021], “for reach respective” should be changed to “for each respective”.
In paragraph [0026], “from the PC core 80” should be changed to “from the PMC core 80”.
In paragraph [0035], “mode transition is request by the PMC” should be changed to “mode transition is requested by the PMC”.
In paragraph [0035], “method stops at 266 . . . .” the stray ellipsis should be removed.
Appropriate correction is required.
Claim Objections
Claim 3, 7- 8 objected to because of the following informalities:
In claim 3: “the operating voltage” should be change to “each respective operating voltage”.
In claim 7: “retain a data” should be change to “retain data”.
In claim 8: “the multiple power domain powers” should be change to “the multiple power domains powers”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected as being indefinite. Claim 1 recites the limitation setting a flag for each of the at least one power domain “to define a previous state for each flag” and subsequently setting the flag for each power domain “to define a requested state for each flag”. The limitations are indefinite because, when more than one power domain is present, the claim establishes multiple previous states and multiple requested states. However, the subsequent limitation recites “comparing the previous state to the requested state” without identifying which previous state is compared with which requested state. It is therefore unclear whether the previous and requested states associated with the same flag or power domain are compared or whether some other comparison is intended. Accordingly, the scope of the claim cannot be determined with reasonable certainty. Applicant is required to clarify the correspondence between the previous state and the requested state being compared.
In addition, the phrase “each power domain comprising the respective mismatch” in claim 1 is unclear because a power domain does not ordinarily “comprise” a mismatch. It is unclear whether the intended limitation is “each power domain having the respective mismatch”. Therefore, the language does not define a certainty and the metes and bounds of the claim are unascertainable. Applicant is required to clarify the limitation.
In claim 2, the limitation “the respective voltage detection level” lacks proper antecedent basis. Claim 1, recites “a low voltage detection level” but does not introduce “a voltage detection level”. Therefore it is not clear whether “a voltage detection level” refers to previously recited “a low voltage detection level” or to a different voltage detection level.
Claim 9 is rejected as being indefinite. Claim 9 recites “each power domain comprising the respective inactive flag”. It is unclear whether this limitation refers to each power domain for which an inactive flag has been set or each power domain whose corresponding flag has an inactive value. Therefore, the language does not define a certainty and the metes and bounds of the claim are unascertainable. Applicant is required to clarify the relationship between each power domain and its corresponding inactive flag.
The same reasons apply to dependent claims 3-8 by virtue of dependency to their independent claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over the article entitled “SRAM Has NoChill: Exploiting Power Domain Separation to Steal On-Chip Secrets” by Mahmod in view of Rajwan et al. (US 2023/0259189 A1).
Regarding claim 1, Mahmod discloses a method for detection and mitigation of volt boot attacks comprising (ll previous classes of attacks (Mahmod, Page. 1053, these systems’ reliance on power domain separation enables a new class of attacks: Volt Boot) and (Mahmod, Page, 1047, the power domain separation through power gating methods and dedicated pins exposed from the SoCs let us shut down the entire system while the small portion that holds sensitive data ‘alive’): applying a respective operating voltage to at least one power domain (Mahmod, Page, 1047, we maintain the domain voltage level from an external voltage probe while disconnecting the main supply line to the PMIC. That is, Volt Boot artificially creates SRAM data retention across a power cycle using a voltage probe in a PCB’s test pad or bare passive component’s lead that is connected to a target memory domain), wherein each respective operating voltage exceeds a low voltage detection level of the respective power domain (Mahmod, Page, 1047, this voltage is well below the nominal supply voltage of the power domain the cells are connoted to. The power domain separation through power gating methods and dedicated pins exposed from the SoCs let us shut down the entire system while the small portion that holds sensitive data ‘alive’); requesting the at least one power domain to transition to a respective lower voltage being less than the low voltage detection level for the respective power domain (Mahmod, Page. 1044, from a power management perspective, these domains are independent and allow full power down at runtime when not needed by the system) and (Mahmod, Page. 1045, some processors allow powering down individual cache components in its L1 memory domain through software);
Mahmod does not explicitly disclose setting a flag for each of the at least one power domain, having the respective operating voltage applied, to define a previous state for each flag;
setting the flag for each of the at least one power domain, having the respective lower voltage applied, to define a requested state for each flag;
comparing the previous state to the requested state to determine a mismatch for each power domain; and
determining an occurrence of a volt boot attack for each power domain comprising the respective mismatch.
However, Rajwan teaches setting a flag for each of the at least one power domain, having the respective operating voltage applied, to define a previous state for each flag (Rajwan, Para. 0046, an identity of the domain, e.g., using four bits thus supporting up to sixteen domains. A “requested-state index” indicative of the requested DVFM state (DVFM setting), e.g., using four bits thus supporting up to sixteen DVFM settings); setting the flag for each of the at least one power domain, having the respective lower voltage applied, to define a requested state for each flag (Rajwan, Para. 0047, a “requested-state index” indicative of the requested DVFM state (DVFM setting), e.g., using four bits thus supporting up to sixteen DVFM settings. The requested-state indices are ordered, such that a larger index corresponds to a state having a higher clock rate and/or higher voltage); comparing the previous state to the requested state to determine a mismatch for each power domain (Rajwan, Para. 0085, each completion notification is received from a certain DVFM controller 56, notifying that a previously-granted state transition was completed) and (Rajwan, Para. 0086, at a checking stage 144, protection circuit 76 checks whether the requested transition or transitions for the next clock cycle potentially traverse an invalid system-level state); and determining an occurrence of a volt boot attack for each power domain comprising the respective mismatch (Rajwan, Para. 0079, protection circuit 76 is able to detect whether requested transitions in a given clock cycle are legitimate, or whether they potentially pass through an invalid system-level state. In the former case, the protection circuit allows the transitions to proceed. In the latter case, the protection circuit initiates a responsive action, e.g., halts SoC 40). Mahmod and Rajwan are considered to be analogous to the claim invention because they are in the same field of security and power management in multi-power-domain system on chip (SoCs). Therefore, it would have been obvious to someone ordinary skill in the art before the effective filling date of the claimed invention to have modified Mahmod to incorporate the teachings of Rajwan to include setting a flag for each of the at least one power domain, having the respective operating voltage applied, to define a previous state for each flag (Rajwan, Para. 0046); setting the flag for each of the at least one power domain, having the respective lower voltage applied, to define a requested state for each flag (Rajwan, Para. 0047); comparing the previous state to the requested state to determine a mismatch for each power domain (Rajwan, Para. 0085) and (Rajwan, Para. 0086); and determining an occurrence of a volt boot attack for each power domain comprising the respective mismatch (Rajwan, Para. 0079). Doing so would aid in determining that performing the requested transitions may potentially traverse an invalid system-level combination (system-level state), the protection circuit initiates a suitable responsive action, e.g., halts at least part of the system. In this manner, the protection circuit avoids both steady-state invalid states (i.e., after the DVFM state transition is completed), and transient invalid states that may be traversed for a short period of time during the transition (Rajwan, Para. 0028).
Regarding claim 2, the combination of Mahmod in view of Rajwan teaches the method of claim 1 further comprising mitigating the volt boot attack by power cycling each of the at least one power domain in response to an occurrence of the volt boot attack for at least one respective power domain (Mahmod, Page. 1052, to defend against the attack, one can eliminate any one of these essential steps) and (Mahmod, Page. 1052, instead of attempting to reset the memory by writing zero to it, we can adopt a simpler hardware-based solution that internally toggles the power of SRAMs at reset), wherein power cycling comprises reducing each operating voltage below the respective voltage detection level followed by increasing each operating voltage above the respective voltage detection level (Mahmod, Table 3, and Page. 1044, data retention voltage is both process variation and data-dependent but is generally much lower than the threshold voltage of either inverter (i.e., the ‘turn on’ voltage). Provided the voltage of a cell is more than or equal to its data retention voltage, the cell retains its state).
Regarding claim 3, the combination of Mahmod in view of Rajwan teaches the method of claim 2 wherein the operating voltage is reduced below the respective voltage detection level for a predefined period of time (Mahmod, Page. 1052, armv8.A suggests that the L2 cache can be reset by pulling nL2RST pin low for 16 cycles) and (Mahmod, Page. 1044, to maintain the positive feedback loop between the two inverters. The voltage required by an SRAM cell to retain the state is called its data retention voltage [20]. Data retention voltage is both process variation and data-dependent but is generally much lower than the threshold voltage of either inverter (i.e., the ‘turn on’ voltage). Provided the voltage of a cell is more than or equal to its data retention voltage, the cell retains its state.) and (Mahmod, Page. 1052, Instead of attempting to reset the memory by writing zero to it, we can adopt a simpler hardware-based solution that internally toggles the power of SRAMs at reset).
Regarding claim 7, the combination of Mahmod in view of Rajwan teaches the method of claim 1 wherein applying the respective operating voltage to exceed the respective low voltage detection level comprises applying a voltage equal to or greater than a voltage level required to retain a data in a storage element powered by the respective power domain (Mahmod, Page. 1044, data retention voltage is both process variation and data-dependent but is generally much lower than the threshold voltage of either inverter (i.e., the ‘turn on’ voltage). Provided the voltage of a cell is more than or equal to its data retention voltage, the cell retains its state) and (Mahmod, Page. 1045, Memory power domain: this domain supplies power to the memories and their associated peripherals. Most SoCs manage main memory, non-volatile memory (e.g., Flash), and L2/L3 caches with this power domain) and (Mahmod, Page. 1049, the memory domain stays in this retention state indefinitely…once the external probe is in place, we disconnect the device from the main power source while our voltage probe keeps the target SRAM active).
Regarding claim 8, the combination of Mahmod in view of Rajwan teaches the method of claim 1 wherein the at least one power domain comprises multiple power domains (Mahmod, Fig. 2), wherein at least one of the multiple power domain powers a volatile storage element (Mahmod, Page. 1044, SRAM is the building block of volatile internal memories, such as caches, iRAM, registers, TLBs, and BTBs, making them one the most common memory in modern computing systems) and (Mahmod, Table 3).
Regarding claim 9, the combination of Mahmod in view of Rajwan teaches the method of claim 1 further comprising setting an inactive flag for each of the at least one power domain not required for a normal mode of operation (Rajwan, Para. 0086, At a checking stage 144, protection circuit 76 checks whether the requested transition or transitions for the next clock cycle potentially traverse an invalid system-level state), and wherein comparing the flag for each of the at least one power domain transitioned to the respective lower voltage excludes each power domain comprising the respective inactive flag (Rajwan, Para. 0082, protection circuit 76 may detect that a given system-level combination of domain-specific power settings is valid, by detecting that (i) a first index, of a domain-specific power setting requested for the first power domain, is lower than a first predefined threshold, and (ii) a second index, of a domain-specific power setting requested for the second power domain, is higher than a second predefined threshold) and (Rajwan, Para. 0080, the protection circuit repeats the disclosed technique only for domains that communicate with one another) and (Rajwan, Para. 0086, at a checking stage 144, protection circuit 76 checks whether the requested transition or transitions for the next clock cycle potentially traverse an invalid system-level state). Therefore, it would have been obvious to someone ordinary skill in the art before the effective filling date of the claimed invention to have modified Mahmod to incorporate the teachings of Rajwan to include the method of claim 1 further comprising setting an inactive flag for each of the at least one power domain not required for a normal mode of operation (Rajwan, Para. 0086), and wherein comparing the flag for each of the at least one power domain transitioned to the respective lower voltage excludes each power domain comprising the respective inactive flag (Rajwan, Para. 0082) and (Rajwan, Para. 0080) and (Rajwan, Para. 0086). Doing so would aid in determining that performing the requested transitions may potentially traverse an invalid system-level combination (system-level state), the protection circuit initiates a suitable responsive action, e.g., halts at least part of the system. In this manner, the protection circuit avoids both steady-state invalid states (i.e., after the DVFM state transition is completed), and transient invalid states that may be traversed for a short period of time during the transition (Rajwan, Para. 0028).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over the article entitled “SRAM Has NoChill: Exploiting Power Domain Separation to Steal On-Chip Secrets” by Mahmod in view of Rajwan et al. (US 2023/0259189 A1) and further in view of Heo et al. (US 2022/0222339 A1), hereinafter Heo.
Regarding claim 4, the combination of Mahmod in view of Rajwan does not explicitly teach the method of claim 2 further comprising returning an apparatus comprising the at least one power domain to a normal mode of operation after mitigating the volt boot attack, in response to a severity flag setting.
However, Heo teaches returning an apparatus comprising the at least one power domain to a normal mode of operation after mitigating the volt boot attack, in response to a severity flag setting (Heo, Para. 0105, the reset signal generator 1400 generates a reset signal RST based on the final low voltage detection flag signal VDET_MERGED. The reset signal RST is provided to the secure processor 1200, and the secure processor 1200 is reset based on the reset signal RST. Accordingly, the secure element 1000 may protect the secure data SDAT from leakage, destruction, or alteration of the secure data SDAT caused by an external attack) and (Heo, Para. 0111. the logic gate (e.g., OR gate) may receive the low voltage detection flag signal, the malfunction detection flag signal, and the POR signal through an inverter (i.e., the second POR signal VPOR′). If any of the low voltage detection flag signal, the malfunction detection flag signal, and the POR signal through the inverter has a high level (YES in operation S140), the low voltage attack detector 1300 may output a final low voltage detection flag signal VLVDET_MERGED having a high level). Mahmod, Rajwan and Heo are considered to be analogous to the claim invention because they are in the same field of security and power management in multi-power-domain system on chip (SoCs). Therefore, it would have been obvious to someone ordinary skill in the art before the effective filling date of the claimed invention to have modified Mahmod and Rajwan to incorporate the teachings of Heo to include returning an apparatus comprising the at least one power domain to a normal mode of operation after mitigating the volt boot attack, in response to a severity flag setting (Heo, Para. 0105) and (Heo, Para. 0111). Doing so would aid in protecting secure data from leakage, destruction, or alteration of secure data by an external attack, and security performance of the secure element 2300 and the electronic system 2000 including the same may be improved (Heo, Para. 0105).
Regarding claim 5, the combination of Mahmod in view of Rajwan does not explicitly teach the method of claim 2 further comprising returning an apparatus comprising the at least one power domain to a non-secure mode of operation after mitigating the volt boot attack, in response to a severity flag setting.
However, Heo teaches returning an apparatus comprising the at least one power domain to a non-secure mode of operation after mitigating the volt boot attack, in response to a severity flag setting (Heo, Para. 0105, the reset signal generator 1400 generates a reset signal RST based on the final low voltage detection flag signal VDET_MERGED. The reset signal RST is provided to the secure processor 1200, and the secure processor 1200 is reset based on the reset signal RST) and (Heo, Para. 0112, when the low voltage detection flag signal, the malfunction detection flag signal, and the POR signal through the inverter all have low levels (NO in operation S140), the secure processor 1200 may operate normally in operation S160). Mahmod, Rajwan and Heo are considered to be analogous to the claim invention because they are in the same field of security and power management in multi-power-domain system on chip (SoCs). Therefore, it would have been obvious to someone ordinary skill in the art before the effective filling date of the claimed invention to have modified Mahmod and Rajwan to incorporate the teachings of Heo to include returning an apparatus comprising the at least returning an apparatus comprising the at least one power domain to a non-secure mode of operation after mitigating the volt boot attack, in response to a severity flag setting (Heo, Para. 0105) and (Heo, Para. 0112). Doing so would aid in protecting secure data from leakage, destruction, or alteration of secure data by an external attack, and security performance of the secure element 2300 and the electronic system 2000 including the same may be improved (Heo, Para. 0105).
Regarding claim 6, the combination of Mahmod in view of Rajwan does not explicitly teach the method of claim 2 further comprising returning an apparatus comprising the at least one power domain in a reset mode of operation after mitigating the volt boot attack, in response to a severity flag setting.
However, Heo teaches returning an apparatus comprising the at least one power domain in a reset mode of operation after mitigating the volt boot attack, in response to a severity flag setting (Heo, Para. 00105, the reset signal generator 1400 generates a reset signal RST based on the final low voltage detection flag signal VDET_MERGED. The reset signal RST is provided to the secure processor 1200, and the secure processor 1200 is reset based on the reset signal RST. Accordingly, the secure element 1000 may protect the secure data SDAT from leakage, destruction, or alteration of the secure data SDAT caused by an external attack) and (Heo, Para. 0106, For example, the reset signal RST may be provided to the secure memory 1100 as well, and the secure memory 1100 may also be reset based on the reset signal RST) and (Heo, Para. 00111, if any of the low voltage detection flag signal, the malfunction detection flag signal, and the POR signal through the inverter has a high level (YES in operation S140), the low voltage attack detector 1300 may output a final low voltage detection flag signal VLVDET_MERGED having a high level) and (Heo, Para. 00112, the reset signal detector 1400 generates the reset signal RST based on the final low voltage detection flag signal VDET_MERGED… when the low voltage detection flag signal, the malfunction detection flag signal, and the POR signal through the inverter all have low levels (NO in operation S140), the secure processor 1200 may operate normally in operation S160). Mahmod, Rajwan and Heo are considered to be analogous to the claim invention because they are in the same field of security and power management in multi-power-domain system on chip (SoCs). Therefore, it would have been obvious to someone ordinary skill in the art before the effective filling date of the claimed invention to have modified Mahmod and Rajwan to incorporate the teachings of Heo to include returning an apparatus comprising the at least one power domain in a reset mode of operation after mitigating the volt boot attack, in response to a severity flag setting (Heo, Para. 00105) and (Heo, Para. 0106) and (Heo, Para. 00111). Doing so would aid in protecting secure data from leakage, destruction, or alteration of secure data by an external attack, and security performance of the secure element 2300 and the electronic system 2000 including the same may be improved (Heo, Para. 0105).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rodgers (US 2008/0086781 A1) teaches a method and system for glitch protection in a secure system are provided. In this regard, the output of an on-chip security operation may be combinatorially compared with an expected output of the security operation. Based on the results of the comparison, one or more signals which may control access to one or more on-chip secure functions may be generated. The security operation may, for example, comprise generating a message digest utilizing a SHA and/or modifying a stored value based on an amount of code being executed. The expected output may comprise a single value or range of values. In this regard, a system may, for example, be protected from glitch attacks causing lines-of code to be skipped and or causing enable signals to be forced to an illegitimate value.
Hanson et al. (US 2019/0079573 A1) teaches a microcontroller system that includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake - up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.
Meunier et al. (US 11,500,403 B2) teaches a system - on - a - chip (SOC) is designed to operate within optimal voltage and frequency ranges. If an SoC is provided power outside of the optimal voltage range, the SoC can be placed in a high - stress state, exposing the chip to a security attack. Embodiments of the present systems and method limit the minimum and maximum voltage supplied to an SoC from a power management integrated circuit (PMIC). Embodiments can also track a number of requests to provide power outside of the optimal range and can signal a warning of repeated attempts to take an SoC outside of the SoC's optimal range, which may be indicative of a malicious attack on the system
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/GITA FARAMARZI/Examiner, Art Unit 2496
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