DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (pub #US 20240196633 A1 ) in view of Jeter (pub # US 20160364345 A1).
Yang discloses an apparatus, comprising: one or more memory dies (high bandwidth memory system 10a shown in figure 1B, details shown in figure 5; elements 240a-d; paragraph 25; “a plurality of stacked memory dies 240”, figure 5); and an interface die (figure 5, element 222) comprising: a 2.5D PHY (PHY1 shown in figure 1b; figure 5, element 202a; paragraph 32, “a first HBM PHY 202a”) communicatively coupled to the one or more memory dies via Through-Wafer Interconnects (TWIs) (figure 5, elements 262; paragraph 49, “a plurality of through silicon vias, TSVs, 262”), wherein the 2.5D PHY is configured to communicate with a host device (figure 5, memory controller 211) via a predefined communication interface (paragraph 35, “the memory controller 211 may normally interoperate with the HBM 200. For example, the MRS 204 may store a burst length BL, a read latency RL, and operation parameter codes associated with the first HBM PHY 202a”); and a 3D PHY (figure 5, element 202b) communicatively coupled to the one or more memory dies via the TWIs (figure 5, elements 262; paragraph 4; “a plurality of through silicon vias (TSVs) 262”), wherein the 3D PHY is configured to communicate with the host device (figure 5, memory controller 211).
Yang does not explicitly disclose the 3D PHY communicating via a customized communication interface. However, Jeter discloses the 3D PHY communicating via a customized communication interface (figure 2B, paragraph 25; “the memory 114 may indicate its particular operating state to the memory controller 104 via the PHY circuit 108 and identify when the memory 114 is transitioning between operating states, which may be communicated before the transition or after the transition; as will be described below, this information may be used by the memory controller 104 to coordinate reconfiguration of the PHY circuit 108 so that the PHY circuit 108 is able to communicate with the memory 114 after the memory 114 transitions to a new operating state”). Furthermore, teachings of Yang and Jeter are from the same field of memory interfaces.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Jeter in the apparatus of Yang to implement, the 3D PHY communicating via a customized communication interface, in order to process memory request more quickly and configure the PHY more efficiently (Jeter, paragraph 41).
Regarding claim 2, the above combination discloses the apparatus of claim 1, wherein the 3D PHY is communicatively coupled to the TWIs via a DRAM Interface Fabric (Yang, paragraph 49).
Regarding claim 3, the above combination discloses the apparatus of claim 1, wherein each of the one or more memory dies comprises respective interface circuitry to communicate with the interface die via the TWIs (Yang, paragraph 49).
Regarding claim 4, the above combination discloses the apparatus of claim 1, wherein the 2.5D PHY is configured to be used for testing the apparatus before the apparatus is coupled to the host device via the 3D PHY (In Yang, examiner notes that the PHY exchanges data, and can be used for testing by transferring testing-related data; the testing appears to be intended use).
Regarding claim 5, the above combination discloses the apparatus of claim 1, wherein the 2.5D PHY is communicatively coupled to the host device via an interposer (link between the host and the memory, shown in figure 1B).
Regarding claim 6, the above combination discloses the apparatus of claim 1, wherein the 3D PHY is communicatively coupled to the host device via a secondary host device (a memory controller on behalf of a host to communicate with the PHY, Yang, paragraph 4), and wherein the secondary host device comprises the customized communication interface (see rejection of claim 1 for rationale to use a customized communication interface).
Regarding claim 7, the above combination discloses the apparatus of claim 6, wherein the secondary host device is configured to be used for testing the apparatus (in Yang, examiner notes that the host exchanges data with the memory device, and can be used for testing by transferring testing-related data; the testing appears to be intended use).
Regarding claim 8, the above combination discloses the apparatus of claim 1, wherein the 3D PHY is communicatively coupled to the host device via a plurality of micro-bumps (a plurality of electrical connectors/contacts as known in the art), and wherein the host device comprises the customized communication interface (see rejection of claim 1 for rationale to use a customized interface).
Regarding claims 9-20, examiner notes that these claims comprise of similar limitations of claims 1-8 above. The same grounds of rejection are applied.
Conclusion
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/SCOTT C SUN/Primary Examiner, Art Unit 2181