DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the Applicant’s preliminary amendments filed on 01/21/2025. Claims 1-20 remain pending in the application. Claims 1, 3, 5-9, 11-17, and 19 have been amended.
Priority
This application is a continuation of International Application No. PCT/CN2022/143285, filed 12/29/2022, claiming priority to Chinese Patent Application No. 202210555101.X, filed 05/19/2022. The priority claim is acknowledged by the Examiner.
Priority documents were electronically received on 12/26/2024.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/29/2025 and 08/28/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Examiner’s Note
The Examiner cites particular columns, paragraphs, figures, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may also apply. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the claim recites, in pertinent part, “the first resource amount is equal to a maximum resource amount corresponding to the slot”. The maximum resource amount corresponding to the slot under its plain meaning reads as: (1) the maximum resource amount corresponding to the physical limit for the slot itself (i.e. the maximum bandwidth possible for a PCIe x16 slot), or (2) the maximum resource amount corresponding to the hardware unit the slot is connected to. A person of ordinary skill in the art would not be able to recognize which of the two is intended to be encompassed by the claim, rendering the metes and bounds of the claim unclear. For purposes of examination, the Examiner assumes the maximum resource amount corresponding to the slot refers to the maximum resource amount corresponding to the hardware unit the slot is connected to.
Regarding claim 3, the claim recites, in pertinent part, “reading, from the connector, the maximum resource amount corresponding to the slot” and is rejected for similar reasons as those of claim 2.
Claim 4 recites, in pertinent part, “reading, from the connector through the resource manager, the maximum resource amount corresponding to the slot” and is rejected for similar reasons as those of claim 2.
Claim 5 recites, in pertinent part, “obtaining, through the resource manager, the maximum resource amount corresponding to the slot” and is rejected for similar reasons as those of claim 2.
Regarding claim 8, the claim recites, in pertinent part, “creating at least two logical interfaces for the hardware unit based on a multiple between the first resource amount and the target resource amount, wherein a quantity of the at least two logical interfaces is equal to the multiple”. The number of “logical interfaces” is equal to “a multiple between the first resource amount and the target resource amount”. It is unclear to a person of ordinary skill in the art whether “a multiple between A and B” is intended to read
A
*
B
, some multiple
c
(
A
+
B
)
, in which case it is further unclear what is to be multiplied, or any scalar multiple between A and B:
A
c
=
B
or
B
c
=
A
. A person of ordinary skill in the art would not recognize what multiple of any amount of resources is related to an amount of logical interfaces, rendering the metes and bounds of the claim unclear to a person of ordinary skill in the art.
Any claim not explicitly mentioned above is rejected due to dependency on a rejected base claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba et al. (US 20160378509 A1) hereafter Venkatasubba in view of Gorai et al. (US 11689411 B1) hereafter Gorai.
Regarding claim 1, Venkatasubba teaches:
A resource allocation method of a circuit board (Fig. 1; motherboard 101, Paragraph 34, method 200), wherein the circuit board is connected to a hardware unit (Fig. 1; peripheral devices 116 are connected to motherboard 101), the hardware unit is configured to provide a hardware resource (Paragraph 30; “Each peripheral device 116 may be communicatively coupled to processor 103 and may generally include any information handling resource”), the method is applied to a basic input/output system (BIOS) of the circuit board (Paragraph 34; “method 200 for collaboration between BIOS 105 and management controller 112”), and the method comprises:
allocating a resource to the hardware unit based on a first resource amount and a second resource amount (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements”, the default allocation corresponding to the first resource amount, the sufficient amount of resources of the peripheral devices corresponding to the second resource amount.);
wherein the first resource amount is a resource amount pre-allocated by the circuit board to the hardware unit (Paragraphs 35-36; “At step 202, after system power on, BIOS 105 may initiate POST, including initialization of a chipset (e.g., PCH 106) and memory 104. At step 204, BIOS 105 may obtain from management controller 112 (e.g., via shared memory and/or appropriate commands) information regarding the resource requirements for peripheral devices 116.”, the initial allocation based on the resource requirements corresponding to the first resource amount, further evidenced by Paragraph 36; “At step 206, BIOS 105 may determine if its default allocation of resources for peripheral devices 116 among processor sockets is sufficient.”);
and the second resource amount is a resource amount needed by the hardware unit (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements. In these and other embodiments, BIOS 105 may reduce the default allocation if peripheral devices 116 require less memory-mapped I/O than the default allocation”, where a “sufficient” amount of resources for the peripheral devices corresponds to the resource amount needed by the hardware unit.).
Venkatasubba does not teach that a request is made.
However, Gorai teaches:
a request is made (Col. 10, lines 21-23; “For example, a hardware implementation may employ a look-up table for modification of storage access requests to secure non-disk data.”).
Venkatasubba and Gorai are considered to be analogous to the claimed invention because they are reasonably pertinent to management and configuration of resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba and Gorai to have the hardware unit make a request for the second resource amount. A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized requests as a well-known concept in the art, whose implementation would yield the predictable result of letting the system know how many resources are required for execution such that the system is able to properly allocate the amount of resources, thereby avoiding starvation or over-allocation of resources.
Claim 17 recites similar limitations as those of claim 1, directed toward an apparatus, additionally reciting a resource allocation unit as performing the claimed allocation. Venkatasubba teaches:
a resource allocation system (Paragraph 33; “the resource requirements information maintained by management controller 112 may be used in a subsequent boot, and if peripheral devices 116 have been added or removed, then management controller 112 may re-retrieve resource requirements. Once the resource requirements have been retrieved by management controller 112, management controller 112 may make such information available to BIOS 105 through shared memory (e.g., within memory 104 or 114) or through commands (e.g., Intelligent Platform Management Interface commands)”, where the BIOS performs the allocation steps, Paragraph 37; “BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements”).
and a field replaceable unit (Paragraph 33; “management controller 112 may, via an I2C bus, read requirements from a field replacement unit (FRU) associated with the peripheral devices.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the management controller as a field replaceable unit with the resource allocation system because Venkatasubba associates FRUs with the devices managed by the controller and provides for the controller to read device requirements from the associated field replaceable units, the implementation of which would yield the predictable benefit of facilitating replacement and maintenance of the controller while retaining the disclosed resource management functionality.
Claim 17 is rejected for similar reasons as those of claim 1.
Regarding claim 2, Venkatasubba in view of Gorai teach the method of claim 1. Venkatasubba teaches:
wherein the circuit board is located in a computer device (Fig. 1; peripheral devices 116 are connected to motherboard 101 which is in a computer device.), the hardware unit is a peripheral device of the computer device (Fig. 1; peripheral devices 116), the hardware unit is connected to the circuit board (Paragraph 19; “As depicted in FIG. 1, information handling system 102 may include a motherboard 101, a network interface 108 communicatively coupled to a processor 103 of motherboard 101, and one or more peripheral devices 116 communicatively coupled to processor 103.”, and further evidenced by Paragraph 30; “As shown in FIG. 1, peripheral devices 116 may also be coupled to processor 113 via an inter-integrated circuit (I2C) bus and/or via a PCIe bus.”.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the disclosed PCIe connection using a PCIe slot on the motherboard because PCIe slots are a well-known conventional interface for connecting peripheral devices to a motherboard, whose implementation would yield the predictable result of providing the disclosed PCIe communication between the peripheral device and the processor.
Gorai teaches:
the first resource amount is equal to a maximum resource amount (Col. 6, lines 60-65; “In addition to specifying the amount of the particular hardware resource that is reserved, the hardware resource allocations, “memory_allocation”: { }, “cpu_allocation”: { }, and “storage_allocation”: { }, may also specify an upper limit to the hardware resource that can be consumed by the resource pool”, where the upper limit to the hardware resource to be consumed corresponds to the first resource amount.).
Claim 18 recites similar limitations as those of claim 2. Claim 18 is rejected for similar reasons as those of claim 2.
Regarding claim 3, Venkatasubba in view of Gorai teach the method of claim 2. Venkatasubba teaches:
wherein the circuit board is connected to a connector (Fig. 1; peripheral devices 116 are connected to motherboard 101), the hardware unit is connected to the slot (Paragraph 19; “As depicted in FIG. 1, information handling system 102 may include a motherboard 101, a network interface 108 communicatively coupled to a processor 103 of motherboard 101, and one or more peripheral devices 116 communicatively coupled to processor 103.”, and further evidenced by Paragraph 30; “As shown in FIG. 1, peripheral devices 116 may also be coupled to processor 113 via an inter-integrated circuit (I2C) bus and/or via a PCIe bus.”.), and before the allocating a resource to the hardware unit based on a first resource amount and a second resource amount (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements.”, which discloses performing an action based on the default resource allocation which is the first resource amount, thereby performing actions prior to the re-allocation step based on both the first and second resource amounts), the method further comprises:
using the read maximum resource amount as the first resource amount (Paragraph 35; “At step 202, after system power on, BIOS 105 may initiate POST, including initialization of a chipset (e.g., PCH 106) and memory 104. At step 204, BIOS 105 may obtain from management controller 112 (e.g., via shared memory and/or appropriate commands) information regarding the resource requirements for peripheral devices 116.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have utilized a connector to connect the circuit board, the hardware unit, and the slot, where the slot is a fitting slot on the circuit board. A person of ordinary skill in the art would have recognized that connectors are a well-known conventional interface for PCIe peripheral devices, and a motherboard connected to a PCIe device through a PCIe bus, as taught by Venkatasubba (Paragraph 30) is commonly implemented through a connector through which a slot on the motherboard is physically connected to the device, the implementation of which would have yielded the predictable result of providing the disclosed PCIe communication while physically coupling the peripheral device to the circuit board through the connector.
Gorai teaches:
reading the maximum resource amount (Col. 6, lines 60-65; “In addition to specifying the amount of the particular hardware resource that is reserved, the hardware resource allocations, “memory_allocation”: { }, “cpu_allocation”: { }, and “storage_allocation”: { }, may also specify an upper limit to the hardware resource that can be consumed by the resource pool”, where the upper limit to the hardware resource to be consumed corresponds to the first resource amount).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have read the maximum resource amount corresponding to the slot through the connector. A person of ordinary skill in the art would have recognized that a peripheral connected through the motherboard would be able to request an upper limit to the resources for consumption by the peripheral utilizing the teachings of Gorai, in conjunction with the physical connections of Venkatasubba, would yield the predictable result of having read the maximum resource amount as the first resource amount through the connector on the circuit board.
Claim 19 recites similar limitations as those of claim 3, performed by the resource allocation unit. Venkatasubba teaches:
a resource allocation system (Paragraph 33; “the resource requirements information maintained by management controller 112 may be used in a subsequent boot, and if peripheral devices 116 have been added or removed, then management controller 112 may re-retrieve resource requirements. Once the resource requirements have been retrieved by management controller 112, management controller 112 may make such information available to BIOS 105 through shared memory (e.g., within memory 104 or 114) or through commands (e.g., Intelligent Platform Management Interface commands)”, where the BIOS performs the allocation steps, Paragraph 37; “BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements”).
and a field replaceable unit (Paragraph 33; “management controller 112 may, via an I2C bus, read requirements from a field replacement unit (FRU) associated with the peripheral devices.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the management controller as a field replaceable unit with the resource allocation system because Venkatasubba associates FRUs with the devices managed by the controller and provides for the controller to read device requirements from the associated field replaceable units, the implementation of which would yield the predictable benefit of facilitating replacement and maintenance of the controller while retaining the disclosed resource management functionality.
Claim 19 is rejected for similar reasons as those of claim 3.
Regarding claim 10, Venkatasubba in view of Gorai teach the method of claim 2. Venkatasubba teaches:
wherein the hardware unit is a high-speed serial computer expansion bus standard PCIe device (Paragraph 4; “a BIOS may reserve a default range of MMIO and legacy I/O to each processor socket. In some cases, the MMIO or legacy I/O capacity is not sufficient for a particular socket, as may be the case if resource-hungry devices (e.g., graphics processing units) are associated with such socket.”, explicitly disclosing a GPU which corresponds to a high-speed serial computer expansion bus standard PCIe device.);
and the resource is a bandwidth (Paragraph 4; “a BIOS may reserve a default range of MMIO and legacy I/O to each processor socket. In some cases, the MMIO or legacy I/O capacity is not sufficient for a particular socket”, I/O capacity corresponding to bandwidth.).
Claims 4-5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Liu et al. (US 20230004508 A1) hereafter Liu.
Regarding claim 4, Venkatasubba in view of Gorai teach the method of claim 3. Venkatasubba teaches:
wherein the circuit board further comprises a resource manager (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements. In these and other embodiments, BIOS 105 may reduce the default allocation if peripheral devices 116 require less memory-mapped I/O than the default allocation”), and the reading, from the connector, the maximum resource amount corresponding to the slot comprises:
Gorai teaches:
reading the maximum resource amount (Col. 6, lines 60-65; “In addition to specifying the amount of the particular hardware resource that is reserved, the hardware resource allocations, “memory_allocation”: { }, “cpu_allocation”: { }, and “storage_allocation”: { }, may also specify an upper limit to the hardware resource that can be consumed by the resource pool”, where the upper limit to the hardware resource to be consumed corresponds to the first resource amount).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have read the maximum resource amount corresponding to the slot through the connector. A person of ordinary skill in the art would have recognized that a peripheral connected through the motherboard would be able to request an upper limit to the resources for consumption by the peripheral utilizing the teachings of Gorai, in conjunction with the physical connections of Venkatasubba, would yield the predictable result of having read the maximum resource amount as the first resource amount through the connector on the circuit board.
While Venkatasubba teaches a BIOS that acts as a resource manager, Venkatasubba in view of Gorai does not teach a distinct resource manager.
However, Liu teaches:
a resource manager (Paragraph 27; “In particular, BIOS 110 may be or include a set of firmware instructions electronically stored within information handling system 100 that allows information handling system 100 to manage various resources and/or perform specific tasks.”).
Venkatasubba, Gorai, and Liu are considered to be analogous to the claimed invention because they are reasonably pertinent to management and configuration of resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Liu to have the BIOS communicate with and rely on a resource manager to perform the resource management operations rather than have the BIOS perform the operations. Delegating resource management to a dedicated component is a known method for separating hardware initialization and configuration from subsequent resource allocation and management, thereby allowing the resource manager to centrally manage resources, the implementation of which would yield the predictable result of allowing the BIOS to provide the relevant hardware/resource information to the resource manager while the resource manager performs the corresponding management operations.
Claim 20 recites similar limitations as those of claim 4, performed by the resource allocation unit. Venkatasubba teaches:
a resource allocation system (Paragraph 33; “the resource requirements information maintained by management controller 112 may be used in a subsequent boot, and if peripheral devices 116 have been added or removed, then management controller 112 may re-retrieve resource requirements. Once the resource requirements have been retrieved by management controller 112, management controller 112 may make such information available to BIOS 105 through shared memory (e.g., within memory 104 or 114) or through commands (e.g., Intelligent Platform Management Interface commands)”, where the BIOS performs the allocation steps, Paragraph 37; “BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements”).
and a field replaceable unit (Paragraph 33; “management controller 112 may, via an I2C bus, read requirements from a field replacement unit (FRU) associated with the peripheral devices.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the management controller as a field replaceable unit with the resource allocation system because Venkatasubba associates FRUs with the devices managed by the controller and provides for the controller to read device requirements from the associated field replaceable units, the implementation of which would yield the predictable benefit of facilitating replacement and maintenance of the controller while retaining the disclosed resource management functionality.
Claim 20 is rejected for similar reasons as those of claim 4.
Regarding claim 5, Venkatasubba in view of Gorai teach the method of claim 2. Venkatasubba teaches:
wherein the hardware unit is connected to the slot (Paragraph 19; “As depicted in FIG. 1, information handling system 102 may include a motherboard 101, a network interface 108 communicatively coupled to a processor 103 of motherboard 101, and one or more peripheral devices 116 communicatively coupled to processor 103.”, and further evidenced by Paragraph 30; “As shown in FIG. 1, peripheral devices 116 may also be coupled to processor 113 via an inter-integrated circuit (I2C) bus and/or via a PCIe bus.”.), the circuit board further comprises a resource manager (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements. In these and other embodiments, BIOS 105 may reduce the default allocation if peripheral devices 116 require less memory-mapped I/O than the default allocation”), and before the allocating a resource to the hardware unit based on a first resource amount and a second resource amount (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements.”, which discloses performing an action based on the default resource allocation which is the first resource amount, thereby performing actions prior to the re-allocation step based on both the first and second resource amounts), the method further comprises:
using the obtained maximum resource amount as the first resource amount (Paragraph 35; “At step 202, after system power on, BIOS 105 may initiate POST, including initialization of a chipset (e.g., PCH 106) and memory 104. At step 204, BIOS 105 may obtain from management controller 112 (e.g., via shared memory and/or appropriate commands) information regarding the resource requirements for peripheral devices 116.”).
Gorai teaches:
obtaining the maximum resource amount (Col. 6, lines 60-65; “In addition to specifying the amount of the particular hardware resource that is reserved, the hardware resource allocations, “memory_allocation”: { }, “cpu_allocation”: { }, and “storage_allocation”: { }, may also specify an upper limit to the hardware resource that can be consumed by the resource pool”, where the upper limit to the hardware resource to be consumed corresponds to the first resource amount).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have obtained the maximum resource amount. A person of ordinary skill in the art would have recognized that a peripheral connected through the motherboard would be able to request an upper limit to the resources for consumption by the peripheral utilizing the teachings of Gorai, in conjunction with the physical connections of Venkatasubba, would yield the predictable result of having read the maximum resource amount as the first resource amount through the connector on the circuit board.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have utilized a connector to connect the circuit board, the hardware unit, and the slot, where the slot is a fitting slot on the circuit board. A person of ordinary skill in the art would have recognized that connectors are a well-known conventional interface for PCIe peripheral devices, and a motherboard connected to a PCIe device through a PCIe bus, as taught by Venkatasubba (Paragraph 30) is commonly implemented through a connector through which a slot on the motherboard is physically connected to the device, the implementation of which would have yielded the predictable result of providing the disclosed PCIe communication while physically coupling the peripheral device to the circuit board through the connector.
While Venkatasubba teaches a BIOS that acts as a resource manager, Venkatasubba in view of Gorai does not teach a distinct resource manager.
However, Liu teaches:
a resource manager (Paragraph 27; “In particular, BIOS 110 may be or include a set of firmware instructions electronically stored within information handling system 100 that allows information handling system 100 to manage various resources and/or perform specific tasks.”).
Venkatasubba, Gorai, and Liu are considered to be analogous to the claimed invention because they are reasonably pertinent to management and configuration of resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Liu to have the BIOS communicate with and rely on a resource manager to perform the resource management operations rather than have the BIOS perform the operations. Delegating resource management to a dedicated component is a known method for separating hardware initialization and configuration from subsequent resource allocation and management, thereby allowing the resource manager to centrally manage resources, the implementation of which would yield the predictable result of allowing the BIOS to provide the relevant hardware/resource information to the resource manager while the resource manager performs the corresponding management operations.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Havlir et al. (US 20230051906 A1) hereafter Havlir.
Regarding claim 6, Venkatasubba in view of Gorai teach the method of claim 2. Venkatasubba teaches:
before the allocating a resource to the hardware unit based on a first resource amount and a second resource amount (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements.”, which discloses performing an action based on the default resource allocation which is the first resource amount, thereby performing actions prior to the re-allocation step based on both the first and second resource amounts), the method further comprises:
Gorai teaches:
reading the plurality of resource amounts from the hardware unit (Col. 6, lines 60-65; “In addition to specifying the amount of the particular hardware resource that is reserved, the hardware resource allocations, “memory_allocation”: { }, “cpu_allocation”: { }, and “storage_allocation”: { }, may also specify an upper limit to the hardware resource that can be consumed by the resource pool”, where the upper limit to the hardware resource to be consumed corresponds to the first resource amount).
Venkatasubba in view of Gorai does not teach wherein the hardware unit comprises a plurality of hardware subunits, the second resource amount comprises a plurality of third resource amounts, each third resource amount of the plurality of third resource amounts corresponds to one hardware subunit in the plurality of hardware subunits, each third resource amount is a maximum resource amount corresponding to the corresponding hardware subunit.
However, Havlir teaches:
wherein the hardware unit comprises a plurality of hardware subunits (Paragraph 48; Sub-units 220, in some embodiments, are scaling units that may be replicated to increase the processing capabilities of a GPU.”), the second resource amount comprises a plurality of third resource amounts (Paragraph 48; “Sub-units 220, in some embodiments, are scaling units that may be replicated to increase the processing capabilities of a GPU”, subunits belonging to a GPU corresponding to a plurality of third resource amounts, the subunits, that comprise a second resource, the GPU itself).
Venkatasubba, Gorai, and Havlir are considered to be analogous to the claimed invention because they are reasonably pertinent to management and configuration of resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Havlir to have represented the second resource as comprising a plurality of third resource amounts corresponding to the plurality of subunits in the hardware unit because allocating and managing a composite hardware unit according to its constituent subunits is a known resource management technique that permits resource availability and allocation to be tracked at a more granular level, as evidenced by Havlir’s utilization of GPU subunits for granular program execution, the implementation of which would yield the predictable result of enabling individual subunits of the hardware to be represented and managed as respective resource amounts. It would have further been obvious to apply the teachings of Gorai of reading resource amounts from the hardware unit to the subunits of Havlir, and have the third resource amount be representative of each of the individual subunits. A person of ordinary skill in the art would recognize that each subunit would have required its own resource allocation, therefore utilizing the allocation/management of composite hardware unit teachings from Havlir would guide a person of ordinary skill in the art to determine resource allocations for each subunit to satisfy the system, yielding the predictable result of preventing resource idling or process starvation.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Havlir, further in view of Soryal et al. (US 20220261265 A1) hereafter Soryal.
Regarding claim 7, Venkatasubba in view of Gorai teach the method of claim 2. Venkatasubba teaches:
allocating a resource to the hardware unit based on a first resource amount and a second resource amount (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements. In these and other embodiments, BIOS 105 may reduce the default allocation if peripheral devices 116 require less memory-mapped I/O than the default allocation”, the first resource amount being the default resource allocation, the second resource amount being the amount required to satisfy resource requirements.).
Gorai teaches:
reading the maximum resource amounts from the hardware unit (Col. 6, lines 60-65; “In addition to specifying the amount of the particular hardware resource that is reserved, the hardware resource allocations, “memory_allocation”: { }, “cpu_allocation”: { }, and “storage_allocation”: { }, may also specify an upper limit to the hardware resource that can be consumed by the resource pool”, where the upper limit to the hardware resource to be consumed corresponds to the maximum resource amount).
Venkatasubba in view of Gorai does not teach wherein the hardware unit comprises a plurality of hardware subunits, the second resource amount comprises a plurality of third resource amounts, each third resource amount of the plurality of third resource amounts corresponds to one hardware subunit in the plurality of hardware subunits, each third resource amount is a maximum resource amount corresponding to the corresponding hardware subunit.
Havlir teaches:
wherein the hardware unit comprises a plurality of hardware subunits (Paragraph 48; Sub-units 220, in some embodiments, are scaling units that may be replicated to increase the processing capabilities of a GPU.”).
Venkatasubba, Gorai, and Havlir are considered to be analogous to the claimed invention because they are reasonably pertinent to management and configuration of resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Havlir to have represented the second resource as comprising a plurality of third resource amounts corresponding to the plurality of subunits in the hardware unit because allocating and managing a composite hardware unit according to its constituent subunits is a known resource management technique that permits resource availability and allocation to be tracked at a more granular level, as evidenced by Havlir’s utilization of GPU subunits for granular program execution, the implementation of which would yield the predictable result of enabling individual subunits of the hardware to be represented and managed as respective resource amounts. It would have further been obvious to apply the teachings of Gorai of reading resource amounts from the hardware unit to the subunits of Havlir, and have the third resource amount be representative of each of the individual subunits. A person of ordinary skill in the art would recognize that each subunit would have required its own resource allocation, therefore utilizing the allocation/management of composite hardware unit teachings from Havlir would guide a person of ordinary skill in the art to determine resource allocations for each subunit to satisfy the system, yielding the predictable result of preventing resource idling or process starvation.
Venkatasubba in view of Gorai, further in view of Havlir does not teach when the first resource amount is greater than or equal to a sum of the plurality of third resource amounts, separately allocating a resource corresponding to the third resource amount.
However, Soryal teaches:
when the first resource amount is greater than or equal to a sum of the plurality of third resource amounts, separately allocating a resource corresponding to the third resource amount to each hardware subunit (Paragraph 37; “It will also be understood that hardware resources 24a through 24n are not limited to any particular number of hardware resources. It will also be understood that while there is a one-to-one mapping of a VM 20 to a FML 22, there is no requirement for a one-to-one mapping of the combination of VM/FML to hardware resources 24a through 24n”, which teaches a one-to-one mapping between resources and hardware, thereby being at least equal to or greater than the sum of the plurality of resource amounts in order to achieve a one-to-one mapping.).
Venkatasubba, Gorai, Havlir, and Soryal are considered to be analogous to the claimed invention because they are reasonably pertinent to resource configuration and management. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, Havlir, and Soryal to have separately allocated resources to each hardware subunit corresponding to the third resource amount of each subunit in response to the first resource amount being greater than or equal to a sub of the plurality of third resource amounts. A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized a one-to-one mapping as a known method in the art, and the comparison of a number of resources to a number of consumers is a known method for identifying whether a one-to-one mapping can be established, whose implementation would yield the predictable result of ensuring that each hardware subunit receives a portion of the first resource in the case where there is a sufficient amount of the first resource to be distributed to the third resources.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Havlir, further in view of Soryal, further in view of Lotfi et al. (US 20190068456 A1) hereafter Lotfi.
Regarding claim 8, Venkatasubba in view of Gorai, further in view of Havlir, further in view of Soryal teach the method of claim 7. Venkatasubba teaches:
before the allocating a resource to the hardware unit based on a first resource amount and a second resource amount (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements.”, which discloses performing an action based on the default resource allocation which is the first resource amount, thereby performing actions prior to the re-allocation step based on both the first and second resource amounts), the method further comprises:
when the first resource amount is greater than a target resource amount (Paragraph 37; “In these and other embodiments, BIOS 105 may reduce the default allocation if peripheral devices 116 require less memory-mapped I/O than the default allocation.”);
Gorai teaches:
reading the maximum resource amounts from the hardware unit (Col. 6, lines 60-65; “In addition to specifying the amount of the particular hardware resource that is reserved, the hardware resource allocations, “memory_allocation”: { }, “cpu_allocation”: { }, and “storage_allocation”: { }, may also specify an upper limit to the hardware resource that can be consumed by the resource pool”, where the upper limit to the hardware resource to be consumed corresponds to the maximum resource amount);
Havlir teaches:
wherein the hardware unit comprises a plurality of hardware subunits (Paragraph 48; Sub-units 220, in some embodiments, are scaling units that may be replicated to increase the processing capabilities of a GPU.”);
performing a subunit mounting operation (Paragraph 65; “FIG. 5 is a diagram illustrating example filling of available hardware slots from multiple logical slots, according to some embodiments. In the illustrated example, control circuitry 215 maps nine logical slots 510A-510I to forty-eight distributed slots (in four groups of four mGPUs) using multiple distribution modes.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, Havlir, and Soryal to have represented the second resource as comprising a plurality of third resource amounts corresponding to the plurality of subunits in the hardware unit because allocating and managing a composite hardware unit according to its constituent subunits is a known resource management technique that permits resource availability and allocation to be tracked at a more granular level, as evidenced by Havlir’s utilization of GPU subunits for granular program execution, the implementation of which would yield the predictable result of enabling individual subunits of the hardware to be represented and managed as respective resource amounts. It would have further been obvious to apply the teachings of Gorai of reading resource amounts from the hardware unit to the subunits of Havlir, and have the third resource amount be representative of each of the individual subunits. A person of ordinary skill in the art would recognize that each subunit would have required its own resource allocation, therefore utilizing the allocation/management of composite hardware unit teachings from Havlir would guide a person of ordinary skill in the art to determine resource allocations for each subunit to satisfy the system, yielding the predictable result of preventing resource idling or process starvation.
Soryal teaches:
storage at a first address (Paragraph 89; “Storage device 440 can be integral to one of the network nodes, such as PGW 426, for example, in the form of internal memory and/or disk drive. It is understood that storage device 440 can include registers suitable for storing address values.”).
A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized storage of addresses in a hardware unit is a known method in the art whose implementation would yield the predictable result of providing the ability to retrieve information from addresses when necessary for execution.
Venkatasubba in view of Gorai, further in view of Havlir, further in view of Soryal does not teach creating at least two logical interfaces for the hardware unit based on a multiple between the first resource amount and the target resource amount, wherein a quantity of the at least two logical interfaces is equal to the multiple, and each logical interface of the at least two logical interfaces is configured to mount one hardware subunit in the hardware unit; and wherein when a hardware subunit is successfully mounted on each of a plurality of logical interfaces in the at least two logical interfaces, the hardware unit comprises the plurality of hardware subunits.
However, Lotfi teaches:
creating at least two logical interfaces for the hardware unit based on a multiple between the first resource amount and the target resource amount, wherein a quantity of the at least two logical interfaces is equal to the multiple, and each logical interface of the at least two logical interfaces is configured to mount one hardware subunit in the hardware unit (Paragraph 91; “FIG. 14 illustrates creating a first VXLAN 1410, connecting second-tier bridge 1330 to the first VXLAN 1410 and to the virtual network interface 1420 of emulated network device 1370, and connecting second-tier bridge 1335 to the first VXLAN 1410 and to the virtual network interface 1425 of emulated network device 1375 in order to create a direct logical connection for the physical link between hardware network devices 1310 and 1315. The direct logical connection mirrors the physical link since the virtual network interfaces 1420 and 1425, that are the endpoints of the direct logical connection, are assigned the same addressing as the physical network interfaces of hardware network devices 1310 and 1315 that are the endpoints of the physical link.”, where the system creates logical connections, corresponding to logical interfaces, for the link between the hardware devices. As it is applying on each hardware subunit that acts as the physical link, the step corresponds to mounting each hardware subunit.).
Venkatasubba, Gorai, Havlir, Soryal, and Lotfi are considered to be analogous to the claimed invention because they are reasonably pertinent to resource configuration and management. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, Havlir, Soryal, and Lotfi to create at least two logical interfaces for the hardware unit based on a multiple between the first resource amount and the target resource amount, wherein a quantity of the at least two logical interfaces is equal to the multiple, and each logical interface of the at least two logical interfaces is configured to mount one hardware subunit in the hardware unit. A person of ordinary skill in the art would have recognized that providing separate logical interfaces for separately mounted hardware subunits is a known approach for independently identifying and managing individual hardware resources, whose implementation would yield the predictable result of permitting individual hardware subunits to be separately accessed and managed through their respective logical interfaces. Further, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious that, upon successful mounting a hardware subunit on each of the plurality of logical interfaces, the hardware unit comprises the plurality of hardware subunits because the claimed condition is a natural and predictable result of successfully completing the respective mounting operations, whose implementation would yield the predictable result of the hardware unit containing the plurality of successfully mounted hardware subunits.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Havlir, further in view of Soryal, further in view of Lotfi, further in view of Liu.
Regarding claim 9, Venkatasubba in view of Gorai, further in view of Havlir, further in view of Soryal, further in view of Lotfi teach the method of claim 8. Venkatasubba teaches:
wherein the circuit board further comprises a processor (Paragraph 19; “As depicted in FIG. 1, information handling system 102 may include a motherboard 101, a network interface 108 communicatively coupled to a processor 103 of motherboard 101), and the separately performing a subunit mounting operation on the at least two logical interfaces comprises:
establishing at least two first links, each first link used for communication between the processor and the corresponding device (Paragraph 30; “Each peripheral device 116 may be communicatively coupled to processor 103 and may generally include any information handling resource. As shown in FIG. 1, peripheral devices 116 may also be coupled to processor 113 via an inter-integrated circuit (I2C) bus and/or via a PCIe bus.”);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the clamed invention to have established a plurality of first links for communication between the processor and the corresponding device. A person of ordinary skill in the art would have recognized that, given hardware units of Venkatasubba are communicatively coupled to the processor, mounted systems on the hardware units would need to have links established for communication between the mounted system(s) and the processor, further motivated by Paragraph 30; “Processor 113 can communicate directly to peripheral devices via PCIe”, in which communication between the mounted device may occur via PCIe lanes.
Havlir teaches:
establishing mapping relationships between the devices, the at least two first links, and at least two hardware subunits (Paragraph 65; “FIG. 5 is a diagram illustrating example filling of available hardware slots from multiple logical slots, according to some embodiments. In the illustrated example, control circuitry 215 maps nine logical slots 510A-510I to forty-eight distributed slots (in four groups of four mGPUs) using multiple distribution modes.”, the links connected to the slots);
Lotfi teaches:
a plurality of logical interfaces (Paragraph 91; “FIG. 14 illustrates creating a first VXLAN 1410, connecting second-tier bridge 1330 to the first VXLAN 1410 and to the virtual network interface 1420 of emulated network device 1370, and connecting second-tier bridge 1335 to the first VXLAN 1410 and to the virtual network interface 1425 of emulated network device 1375 in order to create a direct logical connection for the physical link between hardware network devices 1310 and 1315.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have established mapping relationships between the logical interfaces, the links, and the hardware subunits because maintaining associations between these corresponding resources is a known technique for identifying and managing hardware resources available through respective interfaces, the implementation of which would yield the predictable result enabling each hardware subunit and its associated link to be identified through the corresponding logical interface.
Venkatasubba in view of Gorai, further in view of Havlir, further in view of Soryal, further in view of Lotfi does not teach that the address is allocated by the BIOS.
However, Liu teaches:
the address is allocated by the BIOS (Paragraph 41; “In another example, BIOS 110 may allocate a portion of memory within configuration inventory 210 starting at a memory address corresponding to port 220-2 of root complex 200”.).
Venkatasubba, Gorai, Havlir, Soryal, Lotfi, and Liu are considered to be analogous to the claimed invention because they are reasonably pertinent to resource configuration and management. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, Havlir, Soryal, Lotfi, and Liu and have the address be allocated by the BIOS. A person of ordinary skill in the art would have recognized that assigning addresses to hardware resources is a known technique for identification and accessing resources, whose implementation would yield the predictable result of providing the hardware resource with an address usable by the system for communication and management.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Peng et al. (US 20140040895 A1) hereafter Peng.
Regarding claim 11, Venkatasubba in view of Gorai teach the method of claim 1. Venkatasubba teaches:
wherein the circuit board comprises a plurality of processors (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements.”), the hardware unit is one of the plurality of processors (Paragraph 4; graphics processing unit).
Venkatasubba in view of Gorai does not teach the first resource amount is equal to a total resource amount of the resource divided by a total quantity of the plurality of processors.
However, Peng teaches:
the first resource amount is equal to a total resource amount of the resource divided by a total quantity of the plurality of processors (Paragraph 28; “The calculating module 241 calculates a total sum of the usage rates of each specified resource in the different groups, divides the total sum by a number of the usage rates of each specified resource, and obtains an average usage rate of each specified resource of the virtual machine, such as an average usage rate of the CPU, an average usage rate of the memory, and an average usage rate of the hard disk.”).
Venkatasubba, Gorai, and Peng are considered to be analogous to the claimed invention because they are reasonably pertinent to resource orchestration and management. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Peng to have the first resource amount be equal to a total resource amount of the resource divided by a total quantity of the plurality of processors. A person of ordinary skill in the art would have recognized that an initial resource amount averaged across all existing processors would be an option for setting values to initialize to upon system boot, whose implementation would yield the predictable result of providing a method for a fair initial resource distribution upon boot up of the device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Zou et al. (US 20110010478 A1) hereafter Zou.
Regarding claim 12, Venkatasubba in view of Gorai teach the method of claim 1. Venkatasubba teaches:
wherein the circuit board is located in a computer device (Fig. 1; peripheral devices 116 are connected to motherboard 101 which is in a computer device), at least one peripheral device of the computer device is mounted on the hardware unit, and the circuit board is connected to the at least one peripheral device through at least one slot (Paragraph 19; “As depicted in FIG. 1, information handling system 102 may include a motherboard 101, a network interface 108 communicatively coupled to a processor 103 of motherboard 101, and one or more peripheral devices 116 communicatively coupled to processor 103.”, and further evidenced by Paragraph 30; “As shown in FIG. 1, peripheral devices 116 may also be coupled to processor 113 via an inter-integrated circuit (I2C) bus and/or via a PCIe bus.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the disclosed PCIe connection using a PCIe slot on the motherboard because PCIe slots are a well-known conventional interface for connecting peripheral devices to a motherboard, whose implementation would yield the predictable result of providing the disclosed PCIe communication between the peripheral device and the processor.
Venkatasubba in view of Gorai does not teach when the resource is a bus, the second resource amount is equal to a sum of a total resource amount requested by the at least one peripheral device and a fourth resource amount, wherein the fourth resource amount is a total resource amount pre-allocated by the BIOS for a hot plug function of a target slot, and the target slot is a slot, in the at least one slot, that has a hot plug function.
However, Zou teaches:
when the resource is a bus (Paragraph 30; “For example, the re-balance operation may identify that the bus ranges may be modified for existing devices in the parent and upper level nodes, or that I/O and memory addresses may be moved from a device in the parent and the upper level nodes to meet the resource requirements for the hot-plugged device.”), the second resource amount is equal to a sum of a total resource amount requested by the at least one peripheral device and a fourth resource amount (Paragraph 4; “a basic input/output system (BIOS) may allocate the resources for all on-board (or existing) devices and reserve a limited amount of resources for newly inserted devices (or hot-plugged devices).”, the sum of the total and the reserve corresponding to the sum of the first and fourth resource amounts.), wherein the fourth resource amount is a total resource amount pre-allocated by the BIOS for a hot plug function of a target slot, and the target slot is a slot, in the at least one slot, that has a hot plug function (Paragraph 18; “when a device is hot-plugged (e.g., hot-plugged device 19) into a particular slot (e.g., a hot-plugged device node), there may not be enough available resources that can be provided to the hot-plugged device 19. It may be necessary to find such resources from parent or other upper level device nodes so that the resources can be provided to the hot-plugged device 19”, the available resources that would be allocated corresponding to the amount pre-allocated by the BIOS for the slot having the hot-plug function.).
Venkatasubba, Gorai, and Zou are considered to be analogous to the claimed invention because they are reasonably pertinent to resource orchestration and management. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Zou to have, when the resource is a bus, determine the second resource amount as the sum of the total resource amount requested by the peripheral device and the fourth resource amount preallocated by the BIOS for a hot-plug function of the target slot because accounting for both the resources requested by the peripheral devices and resources reserved for hot-plug function is a known resource allocation technique whose implementation would yield the predictable result of providing sufficient resources to support the peripheral devices while retaining the resources preallocated to hot-plug operations.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Zou, further in view of Havlir, further in view of Rang et al. (US 20230121841 A1) hereafter Rang.
Regarding claim 13, Venkatasubba in view of Gorai, further in view of Zou teach the method of claim 12. Venkatasubba teaches:
peripheral devices (Paragraph 33; “BIOS 105 may obtain from management controller 112 (e.g., via shared memory and/or appropriate commands) information regarding the resource requirements for peripheral devices 116”);
the first peripheral device is a peripheral device, in the at least one peripheral device, that does not comprise a hardware subunit (Paragraph 15; “various input/output (“I/O”) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communication between the various hardware components.” This is further supported by Paragraph 115 of the instant specification, “each logical interface is configured to mount one hardware subunit in the hardware unit.” While a typical mouse has a LMB, RMB, and scroll wheel that are potentially subunit components, one of ordinary skill in the art would not describe these parts as individually mounted to the logical interface. The mouse itself is the peripheral that is mounted as a whole. In other words, the sub-components of a basic mouse does not satisfy the instant specification’s concept of a hardware subunit because the claimed subunit is something that is separately mounted.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the peripheral device as not comprising a separate subunit because Venkatasubba discloses the use of a hardware mouse for I/O operations. A person of ordinary skill in the art would have found it obvious to have the first peripheral device be hardware that does not comprise a hardware subunit because treating a basic I/O mouse as a single resource consuming unit is a known resource management approach whose implementation would yield the predictable result of allocating the required resources to the peripheral device without requiring separate resource allocation for its constituent components.
Venkatasubba in view of Gorai, further in view of Zou does not teach subunits.
However, Havlir teaches:
a plurality of hardware subunits (Paragraph 235; “Graphics unit 2675 may include one or more processors, e.g., one or more graphics processing units (GPU's).”, each GPU corresponding to a hardware subunit.);
the second peripheral device is a peripheral device, in the at least one peripheral device, that comprises a hardware subunit (Paragraph 235; “Graphics unit 2675 may include one or more processors, e.g., one or more graphics processing units (GPU's).”, each GPU in the graphics unit corresponding to a hardware subunit.);
determining the fourth resource amount based on a quantity of target slots in the at least one slot (Paragraph 102; “DRA 620 restarts the allocation machine and re-arbitrates. For various distribution modes, re-arbitration may occur until a sufficient number of hardware slots are available to satisfy the distribution mode.”).
Venkatasubba, Gorai, Zou, and Havlir are considered to be analogous to the claimed invention because they are reasonably pertinent to management and configuration of resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, Zou, and Havlir to have had a plurality of subunits in the hardware unit because allocating and managing a composite hardware unit according to its constituent subunits is a known resource management technique that permits resource availability and allocation to be tracked at a more granular level, as evidenced by Havlir’s utilization of GPU subunits for granular program execution, the implementation of which would yield the predictable result of enabling individual subunits of the hardware to be represented and managed as respective resource amounts. It would have further been obvious to count the number of target slots as the disclosure of Havlir explicitly continues performing re-arbitration until a target number is satisfied, yielding the predictable result of needing to count the number of slots until the system is satisfied.
Venkatasubba in view of Gorai, further in view of Zou, further in view of Havlir does not teach wherein the total resource amount requested by the at least one peripheral device is equal to a sum of a first quantity and a second quantity; wherein the first quantity is a total quantity of first elements, the second quantity is a total quantity of second elements.
However, Rang teaches:
wherein the total amount is equal to a sum of a first quantity and a second quantity (Paragraph 62; “The first aggregation component 204 can add together (sum) the respective quantities (e.g., the respective first values of the respective first counters) stored in the first counters to obtain a total number of releases associated with the data object”);
wherein the first quantity is a total quantity of first elements, the second quantity is a total quantity of second elements (Paragraph 62; “For example, the first aggregation component 204 can access or receive information related to respective quantities stored in the first counters (e.g., the first counter 120, the first counter 124, the first counter 128) of processing elements (e.g., the first processing element 102, the second processing element 104, the Nth processing element 106) within the system 200.”);
using the sum as the total (Paragraph 62; “The first aggregation component 204 can add together (sum) the respective quantities (e.g., the respective first values of the respective first counters) stored in the first counters to obtain a total number of releases associated with the data object.”).
Venkatasubba, Gorai, Zou, Havlir, and Rang are considered to be analogous to the claimed invention because they are reasonably pertinent to resource orchestration and management. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, Zou, Havlir, and Rang to have determined the sum of the total resource amount requested by the at least one peripheral device and the fourth resource amount as the second resource amount by counting the total quantity of peripheral devices and subunits and summing the total because accounting for both the number of peripheral devices, subunits, and slots when determining a total resource request is a known resource management technique for accounting for the respective resource requirements of the devices and their constituent subunits, if any, whose implementation would yield the predictable result of providing a total requested resource amount that reflects all of the devices being managed.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Rang.
Regarding claim 14, Venkatasubba in view of Gorai teach the method of claim 1. Venkatasubba teaches:
wherein the circuit board is located in a computer device (Fig. 1; peripheral devices 116 are connected to motherboard 101 which is in a computer device), at least one peripheral device of the computer device is mounted on the hardware unit (Paragraph 19; “As depicted in FIG. 1, information handling system 102 may include a motherboard 101, a network interface 108 communicatively coupled to a processor 103 of motherboard 101, and one or more peripheral devices 116 communicatively coupled to processor 103.”, and further evidenced by Paragraph 30; “As shown in FIG. 1, peripheral devices 116 may also be coupled to processor 113 via an inter-integrated circuit (I2C) bus and/or via a PCIe bus.”), and when the resource is a memory-mapped input/output address (Paragraph 4; “BIOS may be responsible for enumeration of information handling resources of the information handling system, including assigning identifying information for the information handling resources (e.g., bus/device/function numbers) and allocating memory-mapped input/output (MMIO) and legacy input/output (I/O) resources”);
the second resource amount requested by the at least one peripheral device (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements. In these and other embodiments, BIOS 105 may reduce the default allocation if peripheral devices 116 require less memory-mapped I/O than the default allocation”, the second resource amount being the amount required to satisfy resource requirements).
Venkatasubba in view of Gorai does not teach a sum of resource amounts.
However, Rang teaches:
a sum of resource amounts (Paragraph 62; “For example, the first aggregation component 204 can access or receive information related to respective quantities stored in the first counters (e.g., the first counter 120, the first counter 124, the first counter 128) of processing elements (e.g., the first processing element 102, the second processing element 104, the Nth processing element 106) within the system 200. The first aggregation component 204 can add together (sum) the respective quantities (e.g., the respective first values of the respective first counters) stored in the first counters to obtain a total number of releases associated with the data object.”).
Venkatasubba, Gorai, and Rang are considered to be analogous to the claimed invention because they are reasonably pertinent to resource orchestration and management. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Rang to have determined the sum of the total resource amount requested by the at least one peripheral using it as the second resource amount because accounting for all of the resources needed when determining a total resource request is a known resource management technique for accounting for the respective resource requirements, whose implementation would yield the predictable result of providing a total requested resource amount that reflects all of the devices being managed.
Regarding claim 15, Venkatasubba in view of Gorai, further in view of Rang teach the method of claim 14. Venkatasubba teaches:
wherein before the allocating a resource to the hardware unit based on a first resource amount and a second resource amount (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements.”, which discloses performing an action based on the default resource allocation which is the first resource amount, thereby performing actions prior to the re-allocation step based on both the first and second resource amounts), the method further comprises:
for each peripheral device in the at least one peripheral device (Paragraph 33; management controller 112 may access peripheral devices 116, even when information handling system 102 is offline or powered down (e.g., for access through I2C) or as soon as the information handling system 102 is powered up (e.g., for access through PCIe), and read the resource requirements of the various peripheral devices 116.”, expressly performing actions on each peripheral device.):
when the peripheral device does not comprise a hardware subunit (Paragraph 15; “various input/output (“I/O”) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communication between the various hardware components.” This is further supported by Paragraph 115 of the instant specification, “each logical interface is configured to mount one hardware subunit in the hardware unit.” While a typical mouse has a LMB, RMB, and scroll wheel that are potentially subunit components, one of ordinary skill in the art would not describe these parts as individually mounted to the logical interface. The mouse itself is the peripheral that is mounted as a whole. In other words, the sub-components of a basic mouse does not satisfy the instant specification’s concept of a hardware subunit because the claimed subunit is something that is separately mounted. The Examiner notes that this fulfills the “when the peripheral device does not comprise a hardware subunit, using a maximum resource amount corresponding to the peripheral device as a resource amount requested by the peripheral device” element of two elements separated by “or”.).
Rang teaches:
a sum of resource amounts (Paragraph 62; “For example, the first aggregation component 204 can access or receive information related to respective quantities stored in the first counters (e.g., the first counter 120, the first counter 124, the first counter 128) of processing elements (e.g., the first processing element 102, the second processing element 104, the Nth processing element 106) within the system 200. The first aggregation component 204 can add together (sum) the respective quantities (e.g., the respective first values of the respective first counters) stored in the first counters to obtain a total number of releases associated with the data object.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Rang to have determined the sum of the total resource amount requested by the at least one peripheral that does not contain hardware subunits and using it as the second resource amount because accounting for all of the resources needed when determining a total resource request is a known resource management technique for accounting for the respective resource requirements of all devices, whose implementation would yield the predictable result of providing a total requested resource amount that reflects all of the devices being managed.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Venkatasubba in view of Gorai, further in view of Rang, further in view of Liu.
Regarding claim 16, Venkatasubba in view of Gorai, further in view of Rang teach the method of claim 14. Venkatasubba teaches:
wherein before the allocating a resource to the hardware unit based on a first resource amount and a second resource amount (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements.”, which discloses performing an action based on the default resource allocation which is the first resource amount, thereby performing actions prior to the re-allocation step based on both the first and second resource amounts), the method further comprises:
when the first resource amount is stored, obtaining the stored first resource amount (Paragraph 35; “At step 204, BIOS 105 may obtain from management controller 112 (e.g., via shared memory and/or appropriate commands) information regarding the resource requirements for peripheral devices 116.”);
when the circuit board further comprises a resource manager (Paragraph 37; “At step 208, in response to a determination that the default allocation of resources for peripheral devices 116 among sockets is not sufficient, BIOS 105 may rebalance resources among processor sockets to satisfy resource requirements. In these and other embodiments, BIOS 105 may reduce the default allocation if peripheral devices 116 require less memory-mapped I/O than the default allocation”).
Gorai teaches:
obtaining the first resource amount (Col. 6, lines 60-65; “In addition to specifying the amount of the particular hardware resource that is reserved, the hardware resource allocations, “memory_allocation”: { }, “cpu_allocation”: { }, and “storage_allocation”: { }, may also specify an upper limit to the hardware resource that can be consumed by the resource pool”, where the upper limit to the hardware resource to be consumed corresponds to the first resource amount).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have read the maximum resource amount corresponding to the slot through the connector. A person of ordinary skill in the art would have recognized that a peripheral connected through the motherboard would be able to request an upper limit to the resources for consumption by the peripheral utilizing the teachings of Gorai, in conjunction with the physical connections of Venkatasubba, would yield the predictable result of having read the maximum resource amount as the first resource amount through the connector on the circuit board.
While Venkatasubba teaches a BIOS that acts as a resource manager, Venkatasubba in view of Gorai does not teach a distinct resource manager; or stored in the BIOS.
However, Liu teaches:
stored in the BIOS (Paragraph 35; “In one embodiment, BIOS 110 may store the assigned bus numbers in configuration inventory 210 of root complex 200.”);
a resource manager (Paragraph 27; “In particular, BIOS 110 may be or include a set of firmware instructions electronically stored within information handling system 100 that allows information handling system 100 to manage various resources and/or perform specific tasks.”).
Venkatasubba, Gorai, and Liu are considered to be analogous to the claimed invention because they are reasonably pertinent to management and configuration of resources. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Venkatasubba, Gorai, and Liu to have the BIOS communicate with and rely on a resource manager to perform the resource management operations rather than have the BIOS perform the operations. Delegating resource management to a dedicated component is a known method for separating hardware initialization and configuration from subsequent resource allocation and management, thereby allowing the resource manager to centrally manage resources, the implementation of which would yield the predictable result of allowing the BIOS to provide the relevant hardware/resource information to the resource manager while the resource manager performs the corresponding management operations, such as allowing reads/writes to the resource manager for resource allocation operations. Further, a person of ordinary skill in the art would have recognized that storing resource allocation information in firmware during initialization is a known technique for retaining configuration information used to manage hardware resources, whose implementation would yield the predictable result of making the resource amount available to the BIOS for subsequent resource allocation and configuration.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Williams et al. (US 20180131565 A1) discusses a one-to-many mapping and a many-to-one mapping of virtualized resources to physical resources respectively in which multiple considerations may be taken into consideration (Paragraph 54).
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/KENNETH P TRAN/Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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