DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yadid-Pecht et al. (U.S. PGPUB 2009/0101798).
Regarding claim 1, Yadid-Pecht et al. disclose (Fig. 4) an imaging device comprising: a photoelectric converter (206) that generates signal charge; a charge storage region (234) that stores the signal charge; a first transistor (210) that has a gate coupled to the charge storage region and reads out the signal charge; a feedback amplifier (424) that feeds back an output of the first transistor in a negative feedback manner to the charge storage region, the feedback amplifier having two input terminals, the output of the first transistor being input to a first input terminal (negative terminal), a reference voltage (VrefAR) being input to a second input terminal (positive terminal); and voltage supply circuitry (inherently voltage is supplied by a voltage supply circuit), wherein in a reset operation for discharging the signal charge stored in the charge storage region, the voltage supply circuitry supplies voltages to the second input terminal of the feedback amplifier, and the voltages include at least three voltages different from each other (a ramping voltage 426 has at least three different voltages).
Regarding claims 7, Yadid-Pecht et al. disclose (Fig. 4) an imaging device comprising: a photoelectric converter (206) that generates signal charge; a charge storage region (234) that stores the signal charge; a first transistor (210) that has a gate coupled to the charge storage region and reads out the signal charge; a feedback amplifier (424) that feeds back an output of the first transistor in a negative feedback manner to the charge storage region, the feedback amplifier having two input terminals, the output of the first transistor being input to a first input terminal (negative terminal), a reference voltage (VrefAR) being input to a second input terminal (positive terminal); and voltage supply circuitry (inherently a the voltage is supplied by a voltage supply circuit), wherein in a reset operation for discharging the signal charge stored in the charge storage region, the voltage supply circuitry supplies voltages to the second input terminal of the feedback amplifier, and the voltages have a tapered waveform (ramping voltage 426).
Regarding claims 2, 3, 8 and 9, Yadid-Pecht et al. further disclose (Fig. 4) a second transistor (428) coupled between an output terminal of the feedback amplifier and the charge storage region; the output terminal is coupled to a source or drain of the second transistor.
Allowable Subject Matter
Claims 4-6, 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/THANH LUU/Primary Examiner, Art Unit 2878
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