Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
1. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
2. Claims 1-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The term system voltage is a indefinite term, it could indicate as VDD, VDD2, or any voltage in the whole “memory system” could be considered as a “system voltage.” The office does not know which voltage(s) in the system the applicant is trying to claim, please fix.
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “system voltage” in claims 1-14 are a relative term which renders the claim indefinite. The term “system voltage” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term system voltage is a indefinite term, it could indicate as VDD, VDD2, or any voltage in the whole “memory system” could be considered as a “system voltage.” The office does not know which voltage(s) in the system the applicant is trying to claim, please fix.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claim(s) 1-2, 19-21, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kulkarni et al (Pub. No.: US 2013/0138879).
7. Regarding independent claim 1, Kulkarni et al teaches an apparatus comprising: a data terminal (Fig. 6, I/O0-I/O3) configured to receive data (Fig. 10, I/O0 for example); a setting register (Fig. 6, #624) configured to store (paragraph [0042], lines 17-18) a transition mode setting (paragraph [0042], lines 17-21); and a data input buffer (Fig. 6, #616 for example, or Fig. 7, #702 for example) configured to latch the data on both edges of an internal clock signal (Fig. 6, paragraph [0042], lines 5-9) when the transition mode setting (paragraph [0042], lines 17-21) is inactive (Fig. 6, paragraph [0044], lines 13-18, when high data rate mode is active data is latched on both falling and rising edges, and that means the standard mode is in inactive) and configured to latch the data on one edge of the internal clock signal (Fig. 6, paragraph [0042], lines 3-5) when the transition mode setting (paragraph [0042], lines 17-21) is active, wherein the transition mode setting is active (Fig. 6, paragraph [0044], lines 13-18, when high data rate mode is active data is latched on one falling and rising edges, and that means the standard mode is in active) when a system voltage is changing levels (Fig. 6, when the mode is switching from high data rate mode to standard mode, the command is activated, the data in status register is activated, one of the system voltages must changes its level in order to make a change).
8. Regarding claim 3, Kulkarni teaches the data input buffer (Fig. 6, #616 for example, or Fig. 7, #702 for example) is configured to operate at a single data rate when the transition mode setting is active and to operate at a double data rate when the transition mode setting is inactive (Fig. 7, paragraph [0048], lines 13-24).
9. Regarding claim 4, Kulkarni teaches a transition mode logic circuit configured to set the transition mode setting to an inactive level a set time after it is set to the active level (Fig. 7, paragraph [0048], lines 13-24, when the mode is switching from high data rate mode to standard mode, the command is activated, the data in status register is activated, one of the system voltages must changes its level in order to make a change).
10. Regarding claim 5, Kulkarni teaches a transition mode logic circuit (Fig. 7, #604) configured to set the transition mode setting to an inactive level responsive to the system voltage reaching a stable level (Fig. 7, paragraph [0048], lines 13-24, when the mode is switching from high data rate mode to standard mode, the command is activated, the data in status register is activated, one of the system voltages must changes its level in order to make a change).
11. Regarding claim 6, Kulkarni teaches a memory array (Fig. 7, #610), wherein the latched data in the input buffer (Fig. 7, #702) is written to the memory array while the system voltage is changing levels (see Fig. 7, when data input or output to the storage array, the system voltage must change).
12. Regarding claim 7, Kulkarni teaches the setting register (Fig. 6, #624) is a mode register (see paragraph [0048]).
13. Regarding independent claim 8, Kulkarni teaches a controller (Fig. 4, #404) configured to provide a voltage (see Fig. 4, all controller would provide voltages in order to function, like Vcc in Fig. 8 as an example), a clock signal (Fig.4, CLK), and data (Fig. 4, I/Os); and a memory device (Fig. 4) configured to receive the data at a double data rate (Fig. 4, paragraph [0042], lines 7-8) relative to the clock signal (Fig. 4, CLK) in a first mode (paragraph [0042], lines 7-8, high data rate mode) and at a single data rate (Fig. 4, paragraph [0042], lines 3-5) relative to the clock signal (Fig. 4, CLK) in a second mode (Fig. 4, paragraph [0042], line 3, standard mode), wherein the controller (Fig. 4, #404) is configured to put the memory device (Fig. 4) in the second mode (Fig. 4, paragraph [0042], line 3, standard mode) during a transition period while changing the voltage from a first level to a second level (Fig. 6, when the mode is switching from high data rate mode to standard mode, the command is activated, the data in status register is activated, one of the system voltages must changes its level in order to make a change).
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14. Regarding claim 9, Kulkarni teaches the memory device (Fig. 7) comprises a mode register (Fig. 7, #624) configured to store a transition mode setting (paragraph [0042], lines 17-21), wherein when the transition mode setting is active the device is in the second mode and when the transition mode setting is inactive the device is in the first mode (paragraph [0042], lines 13-18).
15. Regarding claim 10, Kulkarni teaches the controller (Fig. 7, #604) is configured to perform a mode register (Fig. 7, #624) write to set the transition mode setting to the active level at the beginning of the transition period (Fig. 7, paragraph [0048], line 13-24).
16. Regarding claim 11, Kulkarni teaches the memory device (Fig. 7) comprises an internal clock generator configured to generate an internal clock signal based on the clock signal and the voltage (Fig. 15, #1502, Fig. 9, CLK to CLK (POL1)).
17. Regarding claim 12, Kulkarni teaches the memory device (Fig. 7) further comprises an input buffer configured to latch the data on rising and falling edges of the internal clock signal in the first mode and on the rising or the falling edges of the internal clock signal in the second mode (see paragraph [0042], lines 3-13).
18. Regarding claim 13, Kulkarni teaches the controller (Fig. 7, #604) comprises a data controller configured to provide the data at a first rate while the memory device is in the first mode and configured to provide the data at a second rate while the memory device is in the second mode (paragraph [0045], lines 13-18).
19. Regarding claim 14, Kulkarni teaches the controller (Fig. 7, #604) is configured to perform write operations on the memory device during the transition period (paragraph [0048], lines 13-24).
20. Regarding independent claim 15, Kulkarni teaches receiving data on the rising and falling edges of a clock signal at a first time (Fig. 7, paragraph [0042], lines 7-9, paragraph [0045], lines 13-15); activating a transition mode (Fig. 7, paragraph [0048], lines 14-24) based on a transition mode setting (paragraph [0042], lines 17-21); and receiving data on either the rising or the falling edges of the clock signal at a second time when the transition mode is active (Fig. 7, paragraph [0042], lines 3-5, paragraph [0045], lines 15-18).
21. Regarding claim 16, Kulkarni teaches receiving the data at a double data rate at the first time and receiving the data at a single data rate at the second time (paragraph [0048], lines 13-24).
22. Regarding claim 17, Kulkarni teaches setting the transition mode setting to an active state to begin the transition mode (paragraph [0042], lines 16-21, paragraph [0048], lines 13-24).
23. Regarding claim 18, Kulkarni teaches setting the transition mode setting to an inactive state to end the transition mode a set time after setting the transition mode setting to the active state (paragraph [0048], lines 13-24).
24. Regarding claim 19, Kulkarni teaches changing a system voltage from a first level to a second level during the transition mode (Fig. 6, when the mode is switching from high data rate mode to standard mode, the command is activated, the data in status register is activated, one of the system voltages must changes its level in order to make a change).
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25. Regarding claim 20, Kulkarni teaches writing the received data to a memory array while the transition mode is active (paragraph [0048], lines 13-24).
Allowable Subject Matter
26. Claim(s) 6-18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
27. With respect to claims 6, there is no teaching, suggestion, or motivation for combination in the prior art to an internal clock generator configured to provide the internal clock signal based on an external clock signal, wherein the data is received at the input terminal in synchronization with the external clock signal, and wherein a frequency of the internal clock signal is based, in part, on the level of the system voltage.
Conclusion
28. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, KIM (Pub. No: US 2004/0057322).
KIM (Pub. No: US 2004/0057322) shows SDR and DDR mode.
29. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
07/08/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
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