Prosecution Insights
Last updated: April 19, 2026
Application No. 18/951,383

PROTECTING AGAINST LATENT ERRORS USING INTRA-DEVICE PROTECTION DATA

Non-Final OA §103
Filed
Nov 18, 2024
Examiner
PERRY, VICTOR NICHOLAS
Art Unit
2111
Tech Center
2100 — Computer Architecture & Software
Assignee
Pure Storage Inc.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
5 granted / 5 resolved
+45.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
24 currently pending
Career history
29
Total Applications
across all art units

Statute-Specific Performance

§103
79.6%
+39.6% vs TC avg
§102
13.6%
-26.4% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 5 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cologrove (US 2012/0079318 A1) in view of Helmick (US 2021/0081273 A1). In regards to claim 1, Cologrove teaches: A storage system comprising: a plurality of storage devices; and a storage controller, operatively coupled to the plurality of storage devices, configured to: form one or more data segments to be stored in the storage system; (Abstract A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array) wherein the data shards of the first data segment and the at least one intra-device recovery data shard are organized and stored into the flash memory of the first storage device based on fault boundaries in flash architectures for writing to flash cells of the flash memory. (0037, SSDs include read disturb errors) Cologrove fails to teach: and write a first data segment of the one or more data segments to regions of flash memory of a first storage device of the plurality of storage devices; using an erasure code that divides the first data segment into data shards, wherein writing the first data segment comprises calculating at least one intra-device recovery data shard corresponding to the data shards of the first data segment to be stored in the first storage device that protects the data shards; However, Helmick teaches: and write a first data segment of the one or more data segments to regions of flash memory of a first storage device of the plurality of storage devices; (0037, controller 108 may write data to, and read data from, NAND flash memory devices at the page level and erase data from NAND flash memory devices at the block level.) using an erasure code that divides the first data segment into data shards, wherein writing the first data segment comprises calculating at least one intra-device recovery data shard corresponding to the data shards of the first data segment to be stored in the first storage device that protects the data shards; (0075 & 0028, It is noted that, as shown, erasure code module 350 covers a block of 16 shards which is distributed across 16 racks/systems/enclosure 370. data recovery is accomplished, for example, by calculating the XOR of the information recorded on the other drives.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a data storage system including data segments of Cologrove with the teaching of Helmick, which teaches data recovery, erasure, and protection in order to manage errors of storage devices. (Helmick: Abstract, A method of error management includes, in response to a read request for first data from a first storage device of a plurality of storage devices under one or more common data protection schemes, receiving a read uncorrectable indication regarding the first data, obtaining uncorrected data and metadata of an LBA associated with the first data, and obtaining the same LBA from one or more other storage devices of the plurality.) With regards to claim 2, Cologrove in view of Helmick teaches the storage system of claim 1: wherein the first data segment comprises an erase block of the flash memory. (0036, Consequently, all of the Flash memory cells within a block (an erase segment or erase block) are erased together.) With regards to claim 3, Cologrove in view of Helmick teaches the storage system of claim 1: wherein the first data segment is written across multiple erase blocks of the flash memory of the storage device. (0050, An allocation unit within an SSD may include one or more erase blocks within an SSD;) With regards to claim 4, Cologrove in view of Helmick teaches the storage system of claim 1: wherein the at least one intra-device recovery data shard for the first data segment is included within the first data segment along with the data shards of the first data segment. (0055 & 0090, intra-device error recovery data 220 may be stored in one or more pages; the physical layer allocates space in segments which include one segment shard in each device across a set of devices) With regards to claim 5, Cologrove in view of Helmick teaches the storage system of claim 1: wherein the at least one intra-device recovery data shard protecting the data shards of the first data segment is written into a second data segment of the one or more data segments stored on the first storage device. (0010, write a second RAID stripe to the device group according to the second layout, whereby the device group concurrently stores data according to both the first RAID layout and the second RAID layout;) With regards to claim 6, Cologrove in view of Helmick teaches the storage system of claim 1. Cologrove fails to teach: wherein garbage collecting the second data segment comprising the at least one intra-device recovery data shard preserves the at least one intra-device recovery data shard if the first data shard is retained by the storage system. However, Helmick teaches: wherein garbage collecting the second data segment comprising the at least one intra-device recovery data shard preserves the at least one intra-device recovery data shard if the first data shard is retained by the storage system. (0057, the host saves the corrected block's predicted data to the original SSD (e.g., the one that first triggered the uncorrectable event) by using a “write_raw” command that includes the corrected data and new speculatively exchanged data.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a data storage system including data segments of Cologrove with the teaching of Helmick, which teaches data recovery, erasure, and protection in order to manage errors of storage devices. (Helmick: Abstract, A method of error management includes, in response to a read request for first data from a first storage device of a plurality of storage devices under one or more common data protection schemes, receiving a read uncorrectable indication regarding the first data, obtaining uncorrected data and metadata of an LBA associated with the first data, and obtaining the same LBA from one or more other storage devices of the plurality.) With regards to claim 7, Cologrove in view of Helmick teaches the storage system of claim 1: wherein data is written into the first data segment incrementally and where the at least one intra-device recovery data shard for the first data segment is incrementally recalculated and stored into non-volatile random access memory (NVRAM) as data is added into the first data segment. (0105, This table may generally be small enough and have enough updates that updates may be logged in NVRAM.) With regards to claim 8, Cologrove in view of Helmick teaches the storage system of claim 1. Cologrove fails to teach: wherein the fault boundaries are word lines of the flash memory and the data shards and the intra-device recovery data shards are each one or more word lines of the flash memory. However, Helmick teaches: wherein the fault boundaries are word lines of the flash memory and the data shards and the intra-device recovery data shards are each one or more word lines of the flash memory. (0123, performing the error detection operation may indicate that the first codeword is invalid and within an error correction capability of the memory device.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of a data storage system including data segments of Cologrove with the teaching of Helmick, which teaches data recovery, erasure, and protection in order to manage errors of storage devices. (Helmick: Abstract, A method of error management includes, in response to a read request for first data from a first storage device of a plurality of storage devices under one or more common data protection schemes, receiving a read uncorrectable indication regarding the first data, obtaining uncorrected data and metadata of an LBA associated with the first data, and obtaining the same LBA from one or more other storage devices of the plurality.) With regards to claim 9, Cologrove in view of Helmick teaches the storage system of claim 1: wherein the storage controller is further configured to: receive a read request for a data shard of the first data segment; identify an uncorrectable error in the data shard; and recover the data shard comprising the uncorrectable error by utilizing a combination of remaining data shards of the first data segment and the at least one intra-device recovery data shard for the first data segment. (0051 & 0064, one or more state tables may maintain a state of an allocation unit (allocated, free, erased, error), a wear level, and a count of a number of errors (correctable and/or uncorrectable) that have occurred within the allocation unit. SSD may include queues to store at least read requests, write requests, trim requests, erase requests and so forth) With regards to claim 10, Cologrove in view of Helmick teaches the storage system of claim 9: wherein data scrubbing is used to search for the uncorrectable errors as a background operation. (0098, a data scrubber may help identify segments for garbage collection based on this data.) With regards to claim 11, Cologrove in view of Helmick teaches the storage system of claim 10: wherein the data scrubbing is performed by the storage device. (0098, a data scrubber may help identify segments for garbage collection based on this data.) With regards to claim 12, Cologrove in view of Helmick teaches the storage system of claim 1: wherein the first data segment is protected by at least one inter-device recovery segment for a plurality of data segments stored on other storage devices of the plurality of storage devices, wherein the at least one inter-device recovery segment is stored on a separate storage device than the first storage device and the other storage devices storing the plurality of data segments are protected by the inter-device recovery segment. (0054 & 0055, a double parity RAID layout may be replaced with a single parity RAID layout if there is additional intra-device redundancy to protect the data on each device. the intra-device error recovery data 220 may be referred to as intra-device redundancy data 220.) With regards to claim 13, Cologrove in view of Helmick teaches and corresponds to claim 1 and is analyzed accordingly. With regards to claim 14, Cologrove in view of Helmick teaches the method of claim 13 and corresponds to claim 2 as analyzed accordingly. With regards to claim 15, Cologrove in view of Helmick teaches the method of claim 13 and corresponds to claim 3 as analyzed accordingly. With regards to claim 16, Cologrove in view of Helmick teaches the method of claim 13 and corresponds to claim 4 as analyzed accordingly. With regards to claim 17, Cologrove in view of Helmick teaches and corresponds to claim 1 and is analyzed accordingly. With regards to claim 18, Cologrove in view of Helmick teaches the non-transitory computer readable storage medium of claim 17 and corresponds to claim 2 as analyzed accordingly. With regards to claim 19, Cologrove in view of Helmick teaches the non-transitory computer readable storage medium of claim 17 and corresponds to claim 3 as analyzed accordingly. With regards to claim 20, Cologrove in view of Helmick teaches the non-transitory computer readable storage medium of claim 17 and corresponds to claim 4 as analyzed accordingly. Prior Art Made of Record The prior art mode of record and not relied upon is considered pertinent to Applicant’s disclosure: Ayyapureddi (US 2024/0071550 A1): Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can normally be reached Monday - Friday 8:00 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.P./Examiner, Art Unit 2111 /GUERRIER MERANT/ Primary Examiner, Art Unit 2111 2/20/2026
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Prosecution Timeline

Nov 18, 2024
Application Filed
Feb 20, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 3 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 5 resolved cases by this examiner. Grant probability derived from career allow rate.

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