MEMORY DEVICE AND MEMORY SYSTEM

Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Double Patenting Claims 1-2, 6-16, and 18-20 are provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-2, 6-16, and 18-20 of copending Application No. 19/083,443. This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented. Instant application 18/951,652 Copending application 19/083,443 1. A memory device comprising: a memory cell array including a plurality of cell blocks, each cell block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks; a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers. 1. A memory device comprising: a memory cell array including a plurality of cell blocks, each cell block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks; a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers. 2. The memory device of claim 1, wherein the mapping circuit is configured to allocate, according to the output control signal, data output from n cell blocks among 2n cell blocks sharing the activated sub-word line drivers, into the plurality of data pads, where n is an integer greater than or equal to 1. 2. The memory device of claim 1, wherein the mapping circuit is configured to allocate, according to the output control signal, data output from n cell blocks among 2n cell blocks sharing the activated sub-word line drivers, into the plurality of data pads, where n is an integer greater than or equal to 1. 6. The memory device of claim 1, wherein the plurality of cell blocks are grouped into a plurality of cell groups, each group including two adjacent cell blocks, and wherein each of the plurality of cell groups includes: first word lines configured to share first sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a first direction; and second word lines alternately disposed with the first word lines in a second direction intersecting the first direction, and configured to share second sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a direction opposite to the first direction. 6. The memory device of claim 1, wherein the plurality of cell blocks are grouped into a plurality of cell groups, each group including two adjacent cell blocks, and wherein each of the plurality of cell groups includes: first word lines configured to share first sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a first direction; and second word lines alternately disposed with the first word lines in a second direction intersecting the first direction, and configured to share second sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a direction opposite to the first direction. 7. The memory device of claim 6, wherein the mapping circuit is configured to map, according to the output control signal, data output from cell blocks included in one of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 7. The memory device of claim 6, wherein the mapping circuit is configured to map, according to the output control signal, data output from cell blocks included in one of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 8. The memory device of claim 6, wherein the mapping circuit is configured to map, according to the output control signal, data output from a cell block included in each of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 8. The memory device of claim 6, wherein the mapping circuit is configured to map, according to the output control signal, data output from a cell block included in each of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 9. The memory device of claim 1, wherein each of the plurality of cell blocks includes: first word lines configured to share first sub-word line drivers with corresponding word lines of an adjacent cell block disposed in a first direction; and second word lines alternately disposed with the first word lines in a second direction intersecting the first direction, and configured to share second sub-word line drivers with corresponding word lines of an adjacent cell block disposed in a direction opposite to the first direction. 9. The memory device of claim 1, wherein each of the plurality of cell blocks includes: first word lines configured to share first sub-word line drivers with corresponding word lines of an adjacent cell block disposed in a first direction; and second word lines alternately disposed with the first word lines in a second direction intersecting the first direction, and configured to share second sub-word line drivers with corresponding word lines of an adjacent cell block disposed in a direction opposite to the first direction. 10. The memory device of claim 9, wherein the mapping circuit is configured to map, according to the output control signal, data output from one cell block among two cell blocks sharing the activated sub-word line drivers, into the plurality of data pads. 10. The memory device of claim 9, wherein the mapping circuit is configured to map, according to the output control signal, data output from one cell block among two cell blocks sharing the activated sub-word line drivers, into the plurality of data pads. 11. A memory device comprising: a memory cell array including a plurality of cell groups, each group including two adjacent cell blocks among a plurality of cell blocks and sharing sub-word line drivers with adjacent cell groups; a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting a number of bits of data output from cell groups sharing activated sub-word line drivers. 11. A memory device comprising: a memory cell array including a plurality of cell groups, each group including two adjacent cell blocks among a plurality of cell blocks and sharing sub-word line drivers with adjacent cell groups; a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting a number of bits of data output from cell groups sharing activated sub-word line drivers. 12. The memory device of claim 11, wherein each of the plurality of cell groups includes: first word lines configured to share first sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a first direction; and second word lines alternately disposed with the first word lines in a second direction intersecting the first direction, and configured to share second sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a direction opposite to the first direction. 12. The memory device of claim 11, wherein each of the plurality of cell groups includes: first word lines configured to share first sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a first direction; and second word lines alternately disposed with the first word lines in a second direction intersecting the first direction, and configured to share second sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a direction opposite to the first direction. 13. The memory device of claim 12, wherein the mapping circuit is configured to map data output from cell blocks included in one of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 13. The memory device of claim 12, wherein the mapping circuit is configured to map data output from cell blocks included in one of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 14. The memory device of claim 12, wherein the mapping circuit is configured to map data output from a cell block included in each of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 14. The memory device of claim 12, wherein the mapping circuit is configured to map data output from a cell block included in each of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 15. A memory system comprising: a memory module including a plurality of memory devices; and a memory controller configured to provide a command and an address to control the memory module, and output and receive data to and from the memory module, wherein at least one of the plurality of memory devices includes: a memory cell array including a plurality of cell blocks, each block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks; a data input/output circuit configured to input and output the data of the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers. 15. A memory system comprising: a memory module including a plurality of memory devices; and a memory controller configured to provide a command and an address to control the memory module, and output and receive data to and from the memory module, wherein at least one of the plurality of memory devices includes: a memory cell array including a plurality of cell blocks, each block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks; a data input/output circuit configured to input and output the data of the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers. 16. The memory system of claim 15, wherein the mapping circuit is configured to map, according to the output control signal, data output from n cell blocks among 2n cell blocks sharing the activated sub-word line drivers, into the plurality of data pads, where n is an integer greater than or equal to 1. 16. The memory system of claim 15, wherein the mapping circuit is configured to map, according to the output control signal, data output from n cell blocks among 2n cell blocks sharing the activated sub-word line drivers, into the plurality of data pads, where n is an integer greater than or equal to 1. 18. The memory system of claim 15, wherein the plurality of cell blocks are grouped into a plurality of cell groups, each group including two adjacent cell blocks, and wherein each of the plurality of cell groups includes: first word lines configured to share first sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a first direction; and second word lines alternately disposed with the first word lines in a second direction intersecting the first direction, and configured to share second sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a direction opposite to the first direction. 18. The memory system of claim 15, wherein the plurality of cell blocks are grouped into a plurality of cell groups, each group including two adjacent cell blocks, and wherein each of the plurality of cell groups includes: first word lines configured to share first sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a first direction; and second word lines alternately disposed with the first word lines in a second direction intersecting the first direction, and configured to share second sub-word line drivers with corresponding word lines of an adjacent cell group disposed in a direction opposite to the first direction. 19. The memory system of claim 18, wherein the mapping circuit is configured to map, according to the output control signal, data output from cell blocks included in one of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 19. The memory system of claim 18, wherein the mapping circuit is configured to map, according to the output control signal, data output from cell blocks included in one of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 20. The memory system of claim 18, wherein the mapping circuit is configured to map, according to the output control signal, data output from a cell block included in each of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. 20. The memory system of claim 18, wherein the mapping circuit is configured to map, according to the output control signal, data output from a cell block included in each of two cell groups sharing the activated sub-word line drivers, into the plurality of data pads. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm. 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL JOHN KING/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827