DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
1. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-20 of US Patent No. 12/169465.
Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant application is anticipated by patent claim 1 in that claim 1 of the patent contains all the limitations of claim 1 of the instant application. Please see comparison table as below. See In re Goodman(CA FC) 29 USPQ2d 2010(12/3/1993)
And the limitations of the remaining claims 2-20 are found, with minor variations in the recitation of Patent claims 2-17.
Patent (U.S. Patent No. 12,169,465)
Instant Application (18/951,662)
A Peripheral Component Interconnect express (PCIe) device comprising:
A Peripheral Component Interconnect express (PCIe) device comprising:
a Direct Memory Access (DMA) device including a plurality of functions; and
a Direct Memory Access (DMA) device including a plurality of functions; and
a PCIe interface device configured to perform communication between a host and the DMA device and including a reset operation controller configured to:
a PCIe interface device configured to perform communication between a host and the DMA device and configured to:
group, when a plurality of reset signals are received from the host, reset
operations, which are the same type as other of the reset operations corresponding to other of the plurality of reset signals received from the host, determine a processing order of the reset operations, and
perform the reset operations according to the processing order, wherein the grouped reset operations comprise a first reset operation, which is included in reset operations corresponding to a first reset signal having a high priority among the plurality of reset signals, and
receive a plurality of reset signals from the host, performs reset operations corresponding to a first reset signal having a high priority among the plurality of reset signals, and
a second reset operation, which is the same type as the first reset operation and included in reset operations corresponding to a second reset signal having a low priority among the plurality of reset signals,
performs reset operations excluding at least one target reset operation among reset operations corresponding to a second reset signal having a low priority among the plurality of reset signals,
and wherein the reset operation controller: performs the reset operations, which include the first reset operation, corresponding to the first reset signal; and performs reset operations excluding the second reset operation among the reset operations corresponding to the second reset signal, after performing the reset operations corresponding to the first reset signal.
after performing the reset operations corresponding to the first reset signal, and wherein the at least one target reset operation is the same type as at least one reset operation among the reset operations corresponding to the first reset signal.
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “performs reset operations excluding at least one target reset operation among reset operations corresponding to a second reset signal having a low priority among the plurality of reset signals, after performing the reset operations corresponding to the first reset signal.” it is not understood if the target reset operation is corresponding to a second reset signal having low priority? And/Or performs reset operations corresponding to a second reset signal having a low priority after performing the reset operations corresponding to the first reset signal? An appropriated correction is required.
Claim Interpretation
5. This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “configured to” in claims 1-10.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Objections
6. Claims 1-10 are objected to because of the following informalities: independent claim 1, recites configured to: receive, performs, performs. These should be configured to: “receive”, “perform”, “perform”. Appropriate correction is required.
7. Claims 11-17 are also objected to because of the following informalities: independent claim 11, recites the method comprising: receiving, performing, performs. These should be the method comprising: receiving, performing, performing. Appropriate correction is required.
Conclusion
8. The following prior arts is related to the Applicant’s invention.
As per Frank’s reference (Pub. No. US2022/0398154) discloses only the controller includes a direct memory access (DMA) unit and either a drain unit or a drain and drop unit coupled between the DMA and the PCIe bus. Whereas Chiu’s reference (US Patent 10,642,328) discloses only the PCIe physical layer circuit 132 of the host 130 has a reset terminal RESET1# to activate the reset signal but do not explicitly disclose as Applicant’s recites claims, thus the prior arts do not teach the invention as claimed.
Frank et al. (US Pub. No. US2022/0398154) discloses only the controller includes a direct memory access (DMA) unit and either a drain unit or a drain and drop unit coupled between the DMA and the PCIe bus. The controller is configured to receive commands from a host device through a PCIe bus having a MAC, send data to the host device through the PCIe bus, and execute a function level reset (FLR) command.
Chiu et al. (US Patent 10,642,328) disclose invention provides a solid state drive with a reset circuit. The solid state drive is connected with a host through a bus. The host has a first reset terminal. The physical layer circuit is reset according to a level state of the second reset terminal.
Ishida et al. (US Pub. No. US20210042128) disclose when a PCIe interrupt signal arises due to a PCIe reset signal, the PCIe interrupt control unit 312 acquires transmission source information 351 from each of the end points 35. The GPIO 36 to receive a PCIe reset signal representing that the platform 10 has been initialized at a hardware level.
Freking et al. (Pub. No. US20140351484) disclose only receive a request to reset a PCIe link for a first host device, connected to a plurality of downstream PCIe devices the distributed switch. Various reset operations may be associated with corresponding priority values. These priority values could be used to determine which request should be processed, when multiple requests for distinct reset operations are received. The PCIe broadcast component on the sub-switch module could receive a second request to reset the link for the host device 810, the reset to be performed using a second, different operation as cited at paragraph 93.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/STEVEN G SNYDER/Primary Examiner, Art Unit 2184