Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lele et al. (US 20210034095 and Lele hereinafter.).
Regarding claim 1, Lele discloses a system [fig. 1], comprising: a first circuit [106] configured to: receive a clock signal [CLK]; divide the clock signal based on a value of a first divisor [108] to generate a first clock signal [MCLK]; a second circuit [112A] configured to: receive the first clock signal [MCLK on 114A]; and divide the first clock based on a value of a second divisor [114A] to generate a second clock signal [CCLK_1]; and a third circuit [110] configured to: generate a pulse [SC] to cause the first circuit and the second circuit to concurrently change the value of the first divisor and the value of the second divisor [para. 20].
Regarding claim 3, Lele discloses further the system further comprising: a fourth circuit [fig. 2, controller 201, para. 23] configured to provide a new value [para. 17, a MCLK update request] of the first divisor to the first circuit [para. 20] between consecutive activations of the pulse [para. 31].
Regarding claim 10, Lele discloses further comprising: an oscillator [102] circuit configured to generate the clock signal [as shown].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lele in view of Prysby et al. (US 5384816 and Prysby hereinafter.).
Regarding claim 2, Lele discloses all the features regarding claim 1 as indicated above. Lele does not explicitly disclose wherein a width of the pulse corresponds to a period of the first clock signal.
However, Prysby discloses [see claim 4] wherein a width of the pulse [fig. 3, clock output of shaping circuit 14] corresponds to a period of the first clock signal [fig. 3, DIVCLKP]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Lele to include a width of the pulse corresponds to a period of the first clock signal as taught by Prysby to improve clock division performance in a sync circuit.
Claims 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lele in view of Tucker et al. (US 20150311909 A1 and Tucker hereinafter.).
Regarding claim 4, Lele discloses all the features regarding claim 3 as indicated above. Lele does not explicitly disclose wherein the fourth circuit is configured to reduce a supply voltage to the first circuit based on that the value of the first divisor is increased.
However, Tucker discloses wherein the fourth circuit [fig. 2 and 5] is configured to reduce a supply voltage to the first circuit [divider 30a] based on that the value of the first divisor is increased [para. 18]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Lele to include the fourth circuit is configured to reduce a supply voltage to the first circuit based on that the value of the first divisor is increased as taught by Tucker to improve power consumption.
Regarding claim 5, Lele in view of Tucker discloses further wherein the fourth circuit is configured to provide the new value of the first divisor to the first circuit prior to reduction of the supply voltage [Tucker, para. 18].
Regarding claim 6, Lele in view of Tucker discloses further wherein the fourth circuit is configured to provide a new value of the second divisor to the second circuit prior to the reduction of the supply voltage [Tucker, para. 18].
Regarding claim 7, Lele discloses all the features regarding claim 1 as indicated above. Lele does not explicitly disclose further comprising: a fourth circuit configured to increase a supply voltage to the first circuit based on that the value of the first divisor is decreased.
However, Tucker discloses further comprising: a fourth circuit [fig. 2 and 5] configured to increase a supply voltage to the first circuit [fig. 2, divider 30a] based on that the value of the first divisor is decreased [para. 18]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Lele to include further comprising: a fourth circuit configured to increase a supply voltage to the first circuit based on that the value of the first divisor is decreased as taught by Tucker to improve power consumption in a clocking circuit.
Regarding claim 8, Lele in view of Tucker discloses further wherein the fourth circuit is configured to provide a new value of the first divisor to the first circuit after increase of the supply voltage [Tucker, para. 18].
Regarding claim 9, Lele in view of Tucker discloses further wherein the fourth circuit is configured to provide a new value of the second divisor to the second circuit after the increase of the supply voltage [Tucker, para. 18].
Claims 11-13, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lele in view of Yun et al. (US 7594126 B2 and Yun hereinafter.).
Regarding claim 11, Lele discloses a system [fig. 1], comprising: a first circuit [106] configured to: receive a clock signal [CLK]; and divide the clock signal based on a first divisor [108] to generate a first clock signal [MCLK]; and a second circuit [para. 21, SoC controller] configured to: reduce a supply voltage to the first circuit [para. 15-16]. Lele does not explicitly disclose prior to reducing the supply voltage, provide a new value of the first divisor to the first circuit which is larger than a current value of the first divisor.
However, Yun discloses prior to reducing the supply voltage [fig. 3, step S500-S501], provide a new value of the first divisor to the first circuit which is larger than a current value of the first divisor [step S503-S504]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Lele to include prior to reducing the supply voltage, provide a new value of the first divisor to the first circuit which is larger than a current value of the first divisor as taught by Yun to improve operating performance of a clocking circuit
Regarding claim 12, Lele in view of Yun discloses further comprising: a third circuit configured to: receive the first clock signal [Yun, col 6 lines 30-53]; and divide the first clock signal based on a second divisor to generate a second clock signal [Yun, col 6 lines 30-53], wherein the second circuit is configured to: prior to reducing the supply voltage [Yun, fig. 3, step S500-S501], provide a new value of the second divisor to the third circuit which is larger than a current value of the second divisor [Yun, step S503-S504].
Regarding claim 13, Lele in view of Yun discloses further comprising: a fourth circuit [Lele, 110] configured to generate a pulse [Lele, SC] to cause the first circuit and the second circuit to concurrently change the first divisor and the second divisor [Lele, para. 20].
Regarding claim 15, Lele in view of Yun discloses further wherein the second circuit [Lele, fig. 2, controller 201, para. 23] is configured to provide the new value [Lele, para. 17, a MCLK update request] of the first divisor between consecutive activations of the pulse [Lele, para. 20 and 31].
Regarding claim 16, Lele in view of Yun discloses further wherein the second circuit is configured to: increase the supply voltage to the first circuit [Yun, steps S503-S504]; and subsequent to increasing the supply voltage, provide a next new value of the first divisor to the first circuit which is less than the new value of the first divisor [Yun, S505-S506].
Regarding claim 17, Lele in view of Yun discloses further comprising: a third circuit configured to: receive the first clock signal [Yun, S500-S504]; and divide the first clock signal based on a second divisor to generate a second clock signal [Yun, S500-S504], wherein the second circuit is configured to: subsequent to increasing the supply voltage [Yun, S504], provide a new value of the second divisor to the third circuit which is less than a current value of the second divisor [Yun, S505].
Regarding claim 18, Lele in view of Yun discloses further comprising: an oscillator [102] circuit configured to generate the clock signal [as shown].
Regarding claim 19, Lele discloses a system [fig. 1], comprising: a first circuit [106] configured to: receive a clock signal [CLK]; and divide the clock signal based on a first divisor [108] to generate a first clock signal [MCLK]; a second circuit [112A] configured to: receive the first clock signal [as shown]; and divide the first clock signal based on a second divisor [114A] to generate a second clock signal [CCLK_1]; and a third circuit [para. 21, SoC controller] configured to: reduce a supply voltage to the first circuit based on that the first divisor is increased [para. 15-16], wherein the supply voltage is reduced after increase of the first divisor [para. 15-16 and 21]. Lele does not explicitly disclose increase the supply voltage to the first circuit based on that the first divisor is reduced, wherein the supply voltage is increased before reduction of the first divisor.
However, Yun discloses increase the supply voltage to the first circuit based on that the first divisor is reduced [fig. 3, steps S503-505], wherein the supply voltage is increased before reduction of the first divisor [going from S504 to S505]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Lele to include increase the supply voltage to the first circuit based on that the first divisor is reduced, wherein the supply voltage is increased before reduction of the first divisor as taught by Yun to improve operating performance of a clocking circuit
Regarding claim 20, Lele in view of Yun discloses further comprising: a fourth circuit [Lele, 110] configured to generate a pulse [Lele, SC] to synchronize changes of the first divisor and second divisor [Lele, para. 20].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lele in view of Yun further in view of Prysby.
Regarding claim 14, Lele in view of Yun discloses all the features regarding claim 13 as indicated above. Lele in view of Yun does not explicitly disclose wherein a width of the pulse corresponds to a period of the first clock signal.
However, Prysby discloses [claim 4] wherein a width of the pulse [fig. 3, clock output of shaping circuit 14] corresponds to a period of the first clock signal [fig. 3, DIVCLKP]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Lele to include a width of the pulse corresponds to a period of the first clock signal as taught by Prysby to improve clock division performance in a sync circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAMES G YEAMAN/Examiner, Art Unit 2842
/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842
Prosecution Insights