DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 11/19/24. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-14, 16-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mouret et al. (US 20200192414 A1)
Regarding claim 1. Mouret teaches a device [Fig 9, coupled is interpreted as directly connected or connected between intervening elements it is understood that all elements are coupled together since they are part of the same die; it is understood all transistors have at least control terminal, first and second terminal; and it is understood all resistors have at least 1st and 2nd terminal] comprising: a current mirror [115, excluding 410] including a first transistor [130] and a second transistor [120];
a first circuit [400 w/ 320] including a third transistor [410] coupled to the first transistor and a fourth transistor [450] coupled to the second transistor, wherein a control terminal of the fourth transistor is coupled to the third transistor [coupled through R6];
a second circuit [240 w/ 270] coupled to the current mirror and to the fourth transistor; a voltage divider circuit [R3/R4] coupled to the second circuit; and an output transistor [140] coupled to the second transistor and the voltage divider circuit.
Regarding claim 2. Mouret teaches the device of claim 1, wherein: the first transistor includes a first terminal, a second terminal, and a control terminal [terminals as shown in fig 9]; the second transistor includes a first terminal, a second terminal, and a control terminal [terminals as shown in fig 9];
the first terminal of the first transistor is coupled to the first circuit; the second terminal of the first transistor is coupled to the second terminal of the second transistor; and the first terminal of the second transistor is coupled to the first circuit [coupled is interpreted as connected between intervening elements all elements are coupled together since they are part of the same die].
Regarding claim 3. Mouret teaches the device of claim 2, wherein: the third transistor includes a first terminal, a second terminal, and a control terminal; the fourth transistor includes a first terminal, a second terminal, and a control terminal; the control terminal of the fourth transistor is coupled to the second terminal of the third transistor; and the second terminal of the of the fourth transistor is coupled to the second circuit [coupled is interpreted as connected between intervening elements all elements are coupled together since they are part of the same die].
Regarding claim 4. Mouret teaches the device of claim 3, wherein: the first circuit includes a first resistor [R6] and a second resistor [R5]; a first terminal of the first resistor is coupled to the second terminal of the third transistor; a first terminal of the second resistor is coupled to the second terminal of the fourth transistor; and the control terminal of the third transistor is coupled to the second terminal of the first resistor [coupled is interpreted as connected between intervening elements all elements are coupled together since they are part of the same die].
Regarding claim 6. Mouret teaches a circuit [fig 9, coupled is interpreted as directly connected or connected between intervening elements it is understood that all elements are coupled together since they are part of the same die, it is understood all transistors have at least control terminal, first and second terminal and it is understood all resistors have at least 1st and 2nd terminal] comprising:
a first transistor [130] including a first terminal, a second terminal, and a control terminal; a second transistor [120] including a first terminal, a second terminal, and a control terminal, wherein the second terminal of the first transistor is coupled to the second terminal of the second transistor, and the control terminal of the first transistor is coupled to the control terminal of the second transistor [implicit];
a third transistor [410] including a first terminal, a second terminal, and a control terminal; a fourth transistor [450] including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the first terminal of the first transistor, the first terminal of the second transistor is coupled to the first terminal of the second transistor, and the control terminal of the fourth transistor is coupled to the second terminal of the third transistor;
a fifth transistor [240] including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is coupled to the control terminal of the second transistor;
a sixth transistor [230] including a first terminal, a second terminal, and a control terminal, wherein the second terminal of the fifth transistor is coupled to the first terminal and the control terminal of the sixth transistor, the second terminal of the sixth transistor is coupled to the second terminal of the fourth transistor;
a first resistor [340] including a first terminal and a second terminal, wherein the second terminal of the first resistor is coupled to the control terminal of the fifth transistor;
and a seventh transistor [140] including a first terminal, a second terminal, and a control terminal, wherein the control terminal of the seventh transistor is coupled to the first terminal of the fourth transistor, and the first terminal of the seventh transistor is coupled to the first terminal of the first resistor.
Regarding claim 7. Mouret teaches the circuit of claim 6, further comprising: a second resistor [350] including a first terminal and a second terminal.
Regarding claim 8. Mouret teaches the circuit of claim 7, wherein: the second terminal of the second resistor is coupled to a ground [see 150]; and the first terminal of the second resistor is coupled to the second terminal of the first resistor.
Regarding claim 9. Mouret teaches the circuit of claim 8, further comprising: a third resistor [310] including a first terminal coupled to the second terminal of the third transistor; and a fourth resistor [320] including a first terminal coupled to the second terminal of the fourth transistor.
Regarding claim 10. Mouret teaches the circuit of claim 9, further comprising: an eighth transistor [440] including a first terminal, a second terminal, and a control terminal, wherein the control terminal of the eighth transistor is coupled to the control terminal of the second transistor, the first terminal of the eighth transistor, and the first terminal of the fifth transistor.
Regarding claim 11. Mouret teaches a device [Fig 9, coupled is interpreted as directly connected or connected between intervening elements it is understood that all elements are coupled together since they are part of the same die; it is understood all transistors have at least control terminal, first and second terminal; and it is understood all resistors have at least 1st and 2nd terminal] comprising: a current mirror [115, excluding 410] including a first transistor [130] and a second transistor [120]; a first circuit [400 w/ 320] including a third transistor [410] coupled to the first transistor; a second circuit [240 w/ 270] coupled to the current mirror and to the third transistor; a fourth transistor [450]; a voltage divider circuit [R3/R4] coupled to the second circuit and the fourth transistor; and an output transistor [140] coupled to the first transistor and the voltage divider circuit.
Regarding claim 12. Mouret teaches the device of claim 11, wherein: the first transistor includes a first terminal, a second terminal, and a control terminal; the second transistor includes a first terminal, a second terminal, and a control terminal; the first terminal of the first transistor is coupled to the first circuit; the second terminal of the first transistor is coupled to the second terminal of the second transistor; and the first terminal of the second transistor is coupled to the second circuit [coupled is interpreted as connected between intervening elements all elements are coupled together since they are part of the same die].
Regarding claim 13. Mouret teaches the device of claim 12, wherein: the third transistor includes a first terminal, a second terminal, and a control terminal; the first terminal of the third transistor is coupled to the first terminal of the first transistor; and the second terminal of the third transistor is coupled to the second circuit [coupled is interpreted as connected between intervening elements all elements are coupled together since they are part of the same die].
Regarding claim 14. Mouret teaches the device of claim 13, wherein: the first circuit includes a first resistor [R6] and a second resistor [R5]; a first terminal of the first resistor is coupled to the second terminal of the third transistor; a first terminal of the second resistor is coupled to the second terminal of the first resistor; and the control terminal of the third transistor is coupled to the second terminal of the first resistor [coupled is interpreted as connected between intervening elements all elements are coupled together since they are part of the same die].
Regarding claim 16. Mouret teaches a circuit [Fig 9, coupled is interpreted as directly connected or connected between intervening elements it is understood that all elements are coupled together since they are part of the same die; it is understood all transistors have at least control terminal, first and second terminal; and it is understood all resistors have at least 1st and 2nd terminal] comprising: a first transistor [130] including a first terminal, a second terminal, and a control terminal; a second transistor [120] including a first terminal, a second terminal, and a control terminal, wherein the second terminal of the first transistor is coupled to the second terminal of the second transistor, and the control terminal of the first transistor is coupled to the control terminal of the second transistor;
a third transistor [410] including a first terminal, a second terminal, and a control terminal; a fourth transistor [450] including a first terminal, a second terminal, and a control terminal, wherein the control terminal of the fourth transistor is coupled to the first terminal of the third transistor;
a fifth transistor [240] including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is coupled to the control terminal of the second transistor;
a sixth transistor [230] including a first terminal, a second terminal, and a control terminal, wherein the second terminal of the fifth transistor is coupled to the first terminal and the control terminal of the sixth transistor, the second terminal of the sixth transistor is coupled to the second terminal of the third transistor;
and a first resistor [340] including a first terminal and a second terminal, wherein the second terminal of the first resistor is coupled to the control terminal of the fifth transistor.
Regarding claim 17. Mouret teaches the circuit of claim 16, further comprising: a second resistor [350] including a first terminal and a second terminal.
Regarding claim 18. Mouret teaches the circuit of claim 17, wherein: the second terminal of the second resistor is coupled to a ground [see 150]; and the first terminal of the second resistor is coupled to the second terminal of the first resistor.
Regarding claim 19. Mouret teaches the circuit of claim 18, further comprising: a third resistor [310] including a first terminal coupled to the second terminal of the third transistor; and a fourth resistor [320] including a first terminal coupled to the second terminal of the third resistor.
Regarding claim 20. Mouret teaches the circuit of claim 19, wherein: the second terminal of the fourth transistor is coupled to the second terminal of the second transistor and the second terminal of the first transistor [coupled is interpreted as connected between intervening elements all elements are coupled together since they are part of the same die].
Allowable Subject Matter
Claims 5 and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838
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