DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1, 8, and 15 have been amended. Claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 15-20 are objected to because of the following informalities:
“at a first logical” in line 5 of claim 15 should read as “at a first logical level”.
Claims 16-20 are objected to because they are dependent on the objected claims. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 and 20-21 of U.S. Patent No. 12,182,046. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-17 and 20-21 of US Patent No. 12,182,046 teaches all of the limitations of claims 1-20 of the Instant Application.
As per claims 1-20,
Instant Application
US Patent 12,182,046 (US Application 18/119,578)
Claim 1: A memory device comprising: a memory array; and processing logic, operatively coupled with the memory array and a signal line, to perform operations comprising: identifying a period of time during which a logical level of the signal line is maintained at a first logical level; determining that the period of time satisfied a threshold condition indicating that the data transfer is currently suspended; determining, while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level; and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed.
Claim 1: A memory device comprising: a memory array; and processing logic, operatively coupled with the memory array and a plurality of pins, to perform operations comprising: initiating monitoring of a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal; determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition indicating that the data burst is currently suspended; in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin while the data burst is suspended; determining whether the logical level of the first pin changed from the first logical level to a second logical level; and in response to determining that the logical level of the first pin changed from the first logical level to the second logical level, causing warmup cycles to be performed.
Examiner’s Note:
Claim 1 of US Patent No. 12,182,046 teaches the bolded, italicized, and underlined limitations of instant claim 1.
Claim 2: The memory device of claim 1, wherein the operations further comprise maintaining a second signal line operatively coupled with the processing logic at a logical level throughout the data transfer being active and suspended, and wherein the second signal line is used to trigger the data transfer.
Claim 2: The memory device of claim 1, wherein the plurality of pins further comprises a second pin to trigger the data burst, and wherein the operations further comprise maintaining the second pin at a logical level throughout the data burst being active and suspended.
Claim 3: The memory device of claim 2, wherein the second signal line corresponds to one of: a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin.
Claim 3: The memory device of claim 2, wherein the second pin is one of: a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin.
Claim 4: The memory device of claim 1, wherein the period of time corresponds to a pause period that exceeds a threshold period of time.
Claim 4: The memory device of claim 1, wherein determining whether the period of time satisfies the threshold condition comprises determining whether the period of time exceeds a threshold period of time.
Claim 5: The memory device of claim 4, wherein the threshold period of time is a minimum pause window indicating that the data burst is currently suspended.
Claim 5: The memory device of claim 4, wherein the threshold period of time is a minimum pause window indicating that the data burst is currently suspended.
Claim 6: The memory device of claim 1, wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles.
Claim 6: The memory device of claim 1, wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles.
Claim 7: The memory device of claim 1, wherein the operations further comprise initiating monitoring of the logical level of the signal line in response to detecting that the logical level of the signal line is at the first logical level.
Claim 7: The memory device claim 1, wherein the operations further comprise initiating monitoring of the logical level of the first pin in response to detecting that the logical level of the first pin is at the first logical level.
Claim 8: A method comprising: identifying, by a processing device, a period of time during which a logical level of a signal line is maintained at a first logical level; determining, by the processing device, that the period of time satisfies a threshold condition indicating that the data transfer is currently suspended; determining, by the processing device while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level; and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing, by the processing device, warm-up cycles to be performed.
Claim 8: A method comprising: monitoring, by a processing device operatively coupled to a plurality of pins, a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal; determining, by the processing device, whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition; in response to determining that the period of time satisfies the threshold condition, continuing, by the processing device, to monitor the logical level of the first pin; determining, by the processing device, whether the logical level of the first pin changed from the first logical level to a second logical level; and in response to determining that the logical level of the first pin changed from the first logical level to the second logical level, causing warmup cycles to be performed.
Claim 9: The method of claim 8, wherein the plurality of pins further comprises a second pin to trigger the data burst, and wherein the method further comprises maintaining, by the processing device, the second pin at a logical level throughout the data burst being active and suspended.
Examiner’s Note:
Claim 8 of US Patent No. 12,182,046 teaches the bolded, italicized, and underlined limitations of instant claim 8.
Claim 9 of US Patent No. 12,182,046 teaches the bolded and italicized limitations of instant claim 8.
Claim 9: The method of claim 8, further comprising maintaining, by the processing device, a second signal line at a logical level throughout the data transfer being active and suspended, and wherein the second signal line is used to trigger the data transfer.
Claim 9: The method of claim 8, wherein the plurality of pins further comprises a second pin to trigger the data burst, and wherein the method further comprises maintaining, by the processing device, the second pin at a logical level throughout the data burst being active and suspended.
Claim 10: The method of claim 9, wherein the second signal line corresponds to one of: a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin.
Claim 10: The method of claim 9, wherein the second pin is one of: a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin.
Claim 11: The method of claim 8, wherein the period of time corresponds to a pause period that exceeds a threshold period of time.
Claim 11: The method of claim 8, wherein determining whether the period of time satisfies the threshold condition comprises determining whether the period of time exceeds a threshold period of time.
Claim 12: The method of claim 11, wherein the threshold period of time is a minimum pause window indicating that the data burst is currently suspended.
Claim 12: The method of claim 11, wherein the threshold period of time is a minimum pause window indicating that the data burst is currently suspended.
Claim 13: The method of claim 8, wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles.
Claim 13: The method of claim 8, wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles.
Claim 14: The method of claim 8, further comprising initiating, by the processing device, monitoring of the logical level of the signal line in response to detecting that the logical level of the signal line is at the first logical level.
Claim 14: The method of claim 8, further comprising initiating, by the processing device, monitoring of the logical level of the first pin in response to detecting that the logical level of the first pin is at the first logical level.
Claim 15: A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying a period of time during which a logical level of a signal line is maintained at a first logical; determining that the period of time satisfies a threshold condition indicating that the data transfer is currently suspended; determining, while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level; and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed.
Claim 15: A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: detecting that a first pin is at a first logical level while a data burst is active, wherein the first pin is comprised within a plurality of pins operatively coupled to the processing device, and wherein the first pin is associated with at least one of a read enable signal or a data strobe signal; in response to detecting that the first pin is at the first logical level, causing monitoring of a logical level of a first pin to be initiated; determining whether the data burst is being suspended based on a period of time in which the logical level of the first pin is held at the first logical level; in response to determining that the data burst is being suspended, continuing to monitor the logical level of the first pin; determining whether the logical level of the first pin changed from the first logical level to a second logical level; and in response to determining that the logical level of the first pin changed from the first logical level to the second logical level, causing warmup cycles to be performed.
Claim 16: The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise maintaining a second signal line at a logical level throughout the data transfer being active and suspended, and wherein the second signal line is used to trigger the data transfer.
Claim 16: The non-transitory computer-readable storage medium of claim 15, wherein the plurality of pins further comprises a second pin to trigger the data burst, and wherein the operations further comprise maintaining the second pin at a logical level throughout the data burst being active and suspended.
Claim 17: The non-transitory computer-readable storage medium of claim 16, wherein the second signal line corresponds to one of: a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin.
Claim 17: The non-transitory computer-readable storage medium of claim 16, wherein the second pin is one of: a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin.
Claim 18: The non-transitory computer-readable storage medium of claim 15, wherein the period of time corresponds to a pause period that exceeds a threshold period of time, and wherein the threshold period of time is a minimum pause window indicating that the data burst is currently suspended.
Claim 21: The non-transitory computer-readable storage medium of claim 18, wherein the threshold period of time is a minimum pause window indicating that the data burst is currently suspended.
Claim 19: The non-transitory computer-readable storage medium of claim 15, wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles.
Claim 20: The non-transitory computer-readable storage medium of claim 15, wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles.
Claim 20: The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise initiating monitoring of the logical level of the signal line in response to detecting that the logical level of the signal line is at the first logical level.
Claim 15: A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: detecting that a first pin is at a first logical level while a data burst is active, wherein the first pin is comprised within a plurality of pins operatively coupled to the processing device, and wherein the first pin is associated with at least one of a read enable signal or a data strobe signal; in response to detecting that the first pin is at the first logical level, causing monitoring of a logical level of a first pin to be initiated; determining whether the data burst is being suspended based on a period of time in which the logical level of the first pin is held at the first logical level; in response to determining that the data burst is being suspended, continuing to monitor the logical level of the first pin; determining whether the logical level of the first pin changed from the first logical level to a second logical level; and in response to determining that the logical level of the first pin changed from the first logical level to the second logical level, causing warmup cycles to be performed.
Regarding instant claim 1, as indicated in the table above, all the claimed features in instant claim 1 are disclosed in reference claim 1. It is evident from the table that many limitations in instant claim 1 are linguistically comparable to the emphasized limitations in reference claim 1. While the two claims are not identical, instant claim 1 is anticipated by reference claim 1. Claim 1 of US Patent No. 12,182,046 teaches a memory device with a memory array that determines if a logical level of a first pin is held at a first level or switched to a second logical level during a data burst suspension, wherein in response to determining that the first logical level is switched to a second logical level, performing warmup cycles, which claim 1 of the Instant Application also teaches.
Independent claims 8 and 15 of Instant Application are similar to claim 1 of Instant Application and thus instant claim 8 is rejected under similar rationale in view of claims 8 and 9 of US Patent No. 12,182,046 and instant claim 15 is rejected under similar rationale in view of claim 15 of US Patent No. 12,182,046.
Dependent claims 2-7, 9-14, and 16-20 of Instant Application are rejected over claims 1-17 and 20-21 of US Patent No. 12,182,046. See Table Above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-8, 11-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2022/0253090) in view of Thakkar (US 2013/0166795).
Regarding claim 1, Chae teaches a memory device (Fig. 1, Memory device 1000) comprising: a memory array (Fig. 1, Device 100 is a memory array within 1000; Paragraph 0034, device 100 may include a plurality of memory dies including a memory cell array having a plurality of memory cells storing data); and processing logic (Fig. 1, Clock generator 300 contains processing logic, see Figure 8 warm-up operation controller 310 within 300 and pause detector 320 within 300; Paragraph 0039, clock generator 300 may generate, based on the internal clock, a data processing clock signal), operatively coupled with the memory array (Fig. 8, Clock generator 300 outputs clk_dp signal to memory array; Paragraph 0039, clock generator 300 may generate, based on the internal clock, a data processing clock signal… device 100 may perform a data transmission/reception operation to transmit/receive data to/from the external device on the basis of the data processing clock signal) and a signal line (Fig. 8, Int_clk is an internal clock signal line), to perform operations comprising: a period of time during which a logical level of the signal line is maintained at a first logical level (Fig. 6, Pause period of external clock ext_clk causes the internal clock to also have a pause period at a logical low level (i.e. first logical level)); determining, while the transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level (Fig. 8, Clock generator 300 detects that int_clk begins toggling again (i.e. changing from first logical level to second logical level) during the rst_pause (i.e. while transfer is suspended); Paragraph 0096, when the warm-up operation controller 310 detects the internal clock signal INT_CLK to resume toggling after its pause period under a situation that the warm-up enable signal WARM_EN stays disabled); and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed (Fig. 8, In response to internal clock toggling, generate warm_en signal at warm-up operation controller 310 of clock generator 300 to continue performing warm-up operation, see Figure 6 additional warm control required for resume; Paragraph 0096, warm-up operation controller 310 detects the internal clock signal INT_CLK to resume toggling after its pause period… warm-up operation controller 310 may generate, i.e., enable the warm-up enable signal WARM_EN, and the warm-up cycle operation may be performed again).
Chae does not teach the memory device comprising: identifying a period of time during which a logical level of the signal line is maintained at a first logical level; determining that the period of time satisfies a threshold condition indicating that the data transfer is currently suspended.
Thakkar teaches the memory device (Figs. 1 and 2, Memory device contains host interface 102, which are the same embodiment as block B in Figure 2; Paragraph 0026, Storage device 100 includes a controller 101, a host interface 102, and an array of flash memory 103… Paragraph 0033, host 104 (e.g., depicted as system block A) and host interface 102 (e.g., depicted as system block B)) comprising: identifying a period of time during which a logical level of the signal line is maintained at a first logical level (Figs. 2 and 5, Sink signal line is held at a low logical level for a period of time in Figure 5 by interface 202 of system block B in Figure 2 (i.e. the memory device), wherein the sink signal line is only reactivated after interface 202 identifies a period of time has elapsed; Paragraph 0045, interface 202 may have deactivated the _sink signal to suspend reading of data… interface 202 may reactivate the _sink signal after a period of time to inform output streamer interface 201 that data transmission may continue); determining that the period of time satisfies a threshold condition indicating that the data transfer is currently suspended (Fig. 5, Period of time satisfies the threshold condition of the Sink signal line being at a low level, wherein data transfer is currently suspended during the period; Paragraph 0046, The _sink signal is suspended by deactivating the signal for the third clock cycle, and reactivating the signal for the fourth clock cycle… Paragraph 0044, suspends the transmission of the first portion of data until the _sink signal is reactivated).
Chae and Thakkar are analogous art because they are in the same field of endeavor of performing data transfer synchronization between memory controllers and memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae’s memory device to incorporate the teachings of Thakkar and enable a data transfer to be suspended based on a threshold condition where a period in which the first pin of Chae is held at the low logical level.
One of ordinary skill in the art would be motivated to make the modifications in order to increase bandwidth utilization while reducing the number of handshakes required to perform data transfer configurations (See Thakkar: Paragraphs 0030-0032).
Regarding claim 4, Chae in view of Thakkar teaches the memory device of claim 1. Chae teaches the memory device comprising wherein the period of time corresponds to a pause period that exceeds a threshold period of time (Fig. 7, Period of time includes pause detection period and reset period, wherein when the pause detection period expires then warm-up cycle can be performed; Paragraph 0094, warm-up operation controller 310 may generate the warm-up enable signal WARM_EN after a predetermined amount of time has passed).
Regarding claim 5, Chae in view of Thakkar teaches the memory device of claim 4.
Thakkar teaches the memory device comprising wherein determining whether the data burst is being suspended comprises determining whether the period of time exceeds a minimum pause window indicating that the data burst is currently suspended (Fig. 5, Period of time where sink is held is identified to be at one clock cycle; Paragraph 0046, The _sink signal is suspended by deactivating the signal for the third clock cycle, and reactivating the signal for the fourth clock cycle).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae’s memory device to incorporate the teachings of Thakkar and enable a data transfer to be suspended based on a threshold condition where a period in which the first pin of Chae is held at the low logical level.
One of ordinary skill in the art would be motivated to make the modifications in order to increase bandwidth utilization while reducing the number of handshakes required to perform data transfer configurations (See Thakkar: Paragraphs 0030-0032).
Regarding claim 6, Chae in view of Thakkar teaches the memory device of claim 1. Chae teaches the memory device comprising wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles (Fig. 8, In response to internal clock toggling, generate warmup enable signal (warm_en) at warm-up operation controller 310 of clock generator 300 to continue performing warm-up operation, see Figure 6 additional warm control required for resume; Paragraph 0096, warm-up operation controller 310… enable the warm-up enable signal WARM_EN, and the warm-up cycle operation may be performed again).
Regarding claim 7, Chae in view of Thakkar teaches the memory device of claim 1. Chae teaches the memory device comprising wherein the operations further comprise initiating monitoring of the logical level of the signal line in response to detecting that the logical level of the signal line is at the first logical level (Fig. 7, Pause period causes ext_clk and int_clk to be logical low level and clock generator 300 monitors ext_clk and int_clk by counting the number of toggles in response to pause period to determine when to enter resume period; Paragraph 0089, when the data processing clock signal CLK_DP is in a pause state, the memory device 100 may generate the warm-up reset signal RST_PAUSE and disable the count enable signal CNT_EN. More specifically, when the number of toggles of the data processing clock signal CLK_DP is greater than or equal to the predetermined number, the memory device 100 may keep the warm-up enable signal WARM_EN and the count enable signal CNT_EN enabled. On the other hand, when the number of toggles of the data processing clock signal CLK_DP is smaller than the predetermined number, the memory device 100 may generate the warm-up reset signal RST_PAUSE).
Regarding claim 8, Chae teaches a method comprising: by a processing device (Fig. 8, Clock generator 300) based on a period of time during which a logical level of a signal line is maintained at a first logical level (Fig. 8, Clock generator 300 detects a clock pause period using pause detector 320 and generates a rst_pause signal; Paragraph 0095, pause detector 320 may receive the data processing clock signal CLK_DP and determine whether a pause period exists where a toggle of the data processing clock signal CLK_DP is temporarily stopped); determining, by the processing device while the transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level (Fig. 8, Clock generator 300 detects that int_clk begins toggling again (i.e. changing from first logical level to second logical level) during the rst_pause (i.e. while transfer is suspended); Paragraph 0096, when the warm-up operation controller 310 detects the internal clock signal INT_CLK to resume toggling after its pause period under a situation that the warm-up enable signal WARM_EN stays disabled); and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing, by the processing device, warm-up cycles to be performed (Fig. 8, In response to internal clock toggling, generate warm_en signal at warm-up operation controller 310 of clock generator 300 to continue performing warm-up operation, see Figure 6 additional warm control required for resume; Paragraph 0096, warm-up operation controller 310 detects the internal clock signal INT_CLK to resume toggling after its pause period… warm-up operation controller 310 may generate, i.e., enable the warm-up enable signal WARM_EN, and the warm-up cycle operation may be performed again).
Chae does not teach the method comprising: identifying, by a processing device, a period of time during which a logical level of the signal line is maintained at a first logical level; determining, by the processing device, that the period of time satisfies a threshold condition indicating that the data transfer is currently suspended.
Thakkar teaches the method (Figs. 1 and 2, Method performed at the memory device of 102 and system block B, respectively) comprising: identifying, by a processing device (Fig. 2, System block B), a period of time during which a logical level of the signal line is maintained at a first logical level (Figs. 2 and 5, Sink signal line is held at a low logical level for a period of time in Figure 5 by interface 202 of system block B in Figure 2 (i.e. the memory device), wherein the sink signal line is only reactivated after interface 202 identifies a period of time has elapsed; Paragraph 0045, interface 202 may have deactivated the _sink signal to suspend reading of data… interface 202 may reactivate the _sink signal after a period of time to inform output streamer interface 201 that data transmission may continue); determining, by the processing device (Fig. 2, System block B determines the period of time of one cycle where sink signal is held at a low level), that the period of time satisfies a threshold condition indicating that the data transfer is currently suspended (Fig. 5, Period of time satisfies the threshold condition of the Sink signal line being at a low level, wherein data transfer is currently suspended during the period; Paragraph 0046, The _sink signal is suspended by deactivating the signal for the third clock cycle, and reactivating the signal for the fourth clock cycle… Paragraph 0044, suspends the transmission of the first portion of data until the _sink signal is reactivated).
Chae and Thakkar are analogous art because they are in the same field of endeavor of performing data transfer synchronization between memory controllers and memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae’s method to incorporate the teachings of Thakkar and enable a data transfer to be suspended based on a threshold condition where a period in which the first pin of Chae is held at the low logical level.
One of ordinary skill in the art would be motivated to make the modifications in order to increase bandwidth utilization while reducing the number of handshakes required to perform data transfer configurations (See Thakkar: Paragraphs 0030-0032).
Regarding claim 11, Chae in view of Thakkar teaches the method of claim 8. Chae teaches the method comprising wherein the period of time corresponds to a pause period that exceeds a threshold period of time (Fig. 7, Period of time includes pause detection period and reset period, wherein when the pause detection period expires then warm-up cycle can be performed; Paragraph 0094, warm-up operation controller 310 may generate the warm-up enable signal WARM_EN after a predetermined amount of time has passed).
Regarding claim 12, Chae in view of Thakkar teaches the method of claim 11.
Thakkar teaches the method comprising wherein the threshold period of time is a minimum pause window indicating that the data burst is currently suspended (Fig. 5, Period of time where sink is held is identified to be at one clock cycle; Paragraph 0046, The _sink signal is suspended by deactivating the signal for the third clock cycle, and reactivating the signal for the fourth clock cycle).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae’s method to incorporate the teachings of Thakkar and enable a data transfer to be suspended based on a threshold condition where a period in which the first pin of Chae is held at the low logical level.
One of ordinary skill in the art would be motivated to make the modifications in order to increase bandwidth utilization while reducing the number of handshakes required to perform data transfer configurations (See Thakkar: Paragraphs 0030-0032).
Regarding claim 13, Chae in view of Thakkar teaches the method of claim 8. Chae teaches the method comprising wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles (Fig. 8, In response to internal clock toggling, generate warmup enable signal (warm_en) at warm-up operation controller 310 of clock generator 300 to continue performing warm-up operation, see Figure 6 additional warm control required for resume; Paragraph 0096, warm-up operation controller 310… enable the warm-up enable signal WARM_EN, and the warm-up cycle operation may be performed again).
Regarding claim 14, Chae in view of Thakkar teaches the method of claim 8. Chae teaches the method comprising initiating, by the processing device, monitoring of the logical level of the signal line in response to detecting that the logical level of the signal line is at the first logical level (Fig. 7, Pause period causes ext_clk and int_clk to be logical low level and clock generator 300 monitors ext_clk and int_clk by counting the number of toggles in response to pause period to determine when to enter resume period; Paragraph 0089, when the data processing clock signal CLK_DP is in a pause state, the memory device 100 may generate the warm-up reset signal RST_PAUSE and disable the count enable signal CNT_EN. More specifically, when the number of toggles of the data processing clock signal CLK_DP is greater than or equal to the predetermined number, the memory device 100 may keep the warm-up enable signal WARM_EN and the count enable signal CNT_EN enabled. On the other hand, when the number of toggles of the data processing clock signal CLK_DP is smaller than the predetermined number, the memory device 100 may generate the warm-up reset signal RST_PAUSE).
Regarding claim 15, Chae teaches a non-transitory computer-readable storage medium comprising instructions (Fig. 16, Computer system 5000 includes memory 5200, storage 5400, and application processor 5100 that performs instructions) that, when executed by a processing device, cause the processing device (Fig. 8, Clock generator 300 is part of the computer system seen in Fig. 16) to perform operations comprising: based on a period of time during which a logical level of a signal line is maintained at a first logical level (Fig. 8, Clock generator 300 detects a clock pause period using pause detector 320 based on the pause of int_clk and generates a rst_pause signal indicating a pause (i.e. transfer is suspended); Paragraph 0095, pause detector 320 may receive the data processing clock signal CLK_DP and determine whether a pause period exists where a toggle of the data processing clock signal CLK_DP is temporarily stopped); determining, while the transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level (Fig. 8, Clock generator 300 detects that int_clk begins toggling again (i.e. changing from first logical level to second logical level) during the rst_pause (i.e. while transfer is suspended); Paragraph 0096, when the warm-up operation controller 310 detects the internal clock signal INT_CLK to resume toggling after its pause period under a situation that the warm-up enable signal WARM_EN stays disabled); and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed (Fig. 8, In response to internal clock toggling, generate warm_en signal at warm-up operation controller 310 of clock generator 300 to continue performing warm-up operation, see Figure 6 additional warm control required for resume; Paragraph 0096, warm-up operation controller 310 detects the internal clock signal INT_CLK to resume toggling after its pause period… warm-up operation controller 310 may generate, i.e., enable the warm-up enable signal WARM_EN, and the warm-up cycle operation may be performed again).
Chae does not teach the medium comprising: identifying a period of time during which a logical level of the signal line is maintained at a first logical level; determining that the period of time satisfies a threshold condition indicating that the data transfer is currently suspended.
Thakkar teaches the medium (Figs. 1 and 2, Storage device 100 and system block B, respectively, contain memory) comprising: identifying a period of time during which a logical level of the signal line is maintained at a first logical level (Figs. 2 and 5, Sink signal line is held at a low logical level for a period of time in Figure 5 by interface 202 of system block B in Figure 2 (i.e. the memory device), wherein the sink signal line is only reactivated after interface 202 identifies a period of time has elapsed; Paragraph 0045, interface 202 may have deactivated the _sink signal to suspend reading of data… interface 202 may reactivate the _sink signal after a period of time to inform output streamer interface 201 that data transmission may continue); determining that the period of time satisfies a threshold condition indicating that the data transfer is currently suspended (Fig. 5, Period of time satisfies the threshold condition of the Sink signal line being at a low level, wherein data transfer is currently suspended during the period; Paragraph 0046, The _sink signal is suspended by deactivating the signal for the third clock cycle, and reactivating the signal for the fourth clock cycle… Paragraph 0044, suspends the transmission of the first portion of data until the _sink signal is reactivated).
Chae and Thakkar are analogous art because they are in the same field of endeavor of performing data transfer synchronization between memory controllers and memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae’s non-transitory computer-readable storage medium to incorporate the teachings of Thakkar and enable a data transfer to be suspended based on a threshold condition where a period in which the first pin of Chae is held at the low logical level.
One of ordinary skill in the art would be motivated to make the modifications in order to increase bandwidth utilization while reducing the number of handshakes required to perform data transfer configurations (See Thakkar: Paragraphs 0030-0032).
Regarding claim 18, Chae in view of Thakkar teaches the non-transitory computer-readable storage medium of claim 15. Chae teaches the memory device comprising wherein the period of time corresponds to a pause period that exceeds a threshold of time (Fig. 7, Period of time includes pause detection period and reset period, wherein when the pause detection period expires then warm-up cycle can be performed; Paragraph 0094, warm-up operation controller 310 may generate the warm-up enable signal WARM_EN after a predetermined amount of time has passed).
Thakkar teaches the memory device comprising wherein determining whether the data burst is being suspended comprises determining whether the period of time exceeds a minimum pause window indicating that the data burst is currently suspended (Fig. 5, Period of time where sink is held is identified to be at one clock cycle; Paragraph 0046, The _sink signal is suspended by deactivating the signal for the third clock cycle, and reactivating the signal for the fourth clock cycle).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae’s non-transitory computer-readable storage medium to incorporate the teachings of Thakkar and enable a data transfer to be suspended based on a threshold condition where a period in which the first pin of Chae is held at the low logical level.
One of ordinary skill in the art would be motivated to make the modifications in order to increase bandwidth utilization while reducing the number of handshakes required to perform data transfer configurations (See Thakkar: Paragraphs 0030-0032).
Regarding claim 19, Chae in view of Thakkar teaches the non-transitory computer-readable storage medium of claim 15. Chae teaches the non-transitory computer-readable storage medium comprising wherein causing warmup cycles to be performed comprises issuing a warmup enable signal that initiates the warmup cycles (Fig. 8, In response to internal clock toggling, generate warmup enable signal (warm_en) at warm-up operation controller 310 of clock generator 300 to continue performing warm-up operation, see Figure 6 additional warm control required for resume; Paragraph 0096, warm-up operation controller 310… enable the warm-up enable signal WARM_EN, and the warm-up cycle operation may be performed again).
Regarding claim 20, Chae in view of Thakkar teaches the non-transitory computer-readable storage medium of claim 15. Chae teaches the non-transitory computer-readable storage medium comprising wherein the operations further comprise initiating monitoring of the logical level of the signal line in response to detecting that the logical level of the signal line is at the first logical level (Fig. 7, Pause period causes ext_clk and int_clk to be logical low level and clock generator 300 monitors ext_clk and int_clk by counting the number of toggles in response to pause period to determine when to enter resume period; Paragraph 0089, when the data processing clock signal CLK_DP is in a pause state, the memory device 100 may generate the warm-up reset signal RST_PAUSE and disable the count enable signal CNT_EN. More specifically, when the number of toggles of the data processing clock signal CLK_DP is greater than or equal to the predetermined number, the memory device 100 may keep the warm-up enable signal WARM_EN and the count enable signal CNT_EN enabled. On the other hand, when the number of toggles of the data processing clock signal CLK_DP is smaller than the predetermined number, the memory device 100 may generate the warm-up reset signal RST_PAUSE).
Claims 2-3, 9-10, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chae (US 2022/0253090) in view of Thakkar (US 2013/0166795) and further in view of Redaelli (US 2009/0238001).
Regarding claim 2, Chae in view of Thakkar teaches the memory device of claim 2. Neither Chae nor Thakkar teaches the memory device comprising wherein the operations further comprise maintaining a second signal line operatively coupled with the processing logic at a logical level throughout the data transfer being active and suspended, and wherein the second signal line is used to trigger the data transfer.
Redaelli teaches the memory device comprising wherein the operations further comprise maintaining a second signal line operatively coupled with the processing logic at a logical level throughout the data transfer being active and suspended (Fig. 11, Chip enable signal line operates at a logic level when data transfer is active or waiting (i.e. suspended, see Figure 10, wait period 108 asserted and de-asserted when chip enable 101 is at a logical low level); Paragraph 0084, Following a latency period (see WAIT signal 108), the synchronous burst mode read operation resumes (see CLK signal 106, CE# signal 101), and wherein the second signal line is used to trigger the data transfer (Fig. 11, Chip enable (CE) pin is used to perform a data burst access; Paragraph 0068, when a flash memory is operated in Synchronous Burst access, data read from the memory array may be output in bursts synchronized with the clock signal 76 on the clock [CLK] pin. To start the read cycle, the CE# signal 71 may be asserted to enable read operations).
Chae and Redaelli are analogous art because they are in the same field of endeavor of controlling data transfer via a communication bus between memory controllers and memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae/Thakkar’s memory device to incorporate the teachings of Redaelli and enable the data burst to be triggered based on a chip enable signal.
One of ordinary skill in the art would be motivated to make the modifications in order to increase flexibility in providing a high-speed connection to a memory while increasing read performance (See Redaelli: Paragraph 0018).
Regarding claim 3, the combination of Chae/Thakkar/Redaelli teaches the memory device of claim 2.
Redaelli teaches the memory device comprising wherein the second pin is one of a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin (Fig. 11, Chip enable (CE) pin is used to perform a data burst access; Paragraph 0068, when a flash memory is operated in Synchronous Burst access, data read from the memory array may be output in bursts synchronized with the clock signal 76 on the clock [CLK] pin. To start the read cycle, the CE# signal 71 may be asserted to enable read operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae/Thakkar’s memory device to incorporate the teachings of Redaelli and enable the data burst to be triggered based on a chip enable signal.
One of ordinary skill in the art would be motivated to make the modifications in order to increase flexibility in providing a high-speed connection to a memory while increasing read performance (See Redaelli: Paragraph 0018).
Regarding claim 9, Chae in view of Thakkar teaches the method of claim 8. Neither Chae nor Thakkar teaches the method further comprising maintaining a second signal line operatively coupled with the processing logic at a logical level throughout the data transfer being active and suspended, and wherein the second signal line is used to trigger the data transfer.
Redaelli teaches the method further comprising maintaining a second signal line operatively coupled with the processing logic at a logical level throughout the data transfer being active and suspended (Fig. 11, Chip enable signal line operates at a logic level when data transfer is active or waiting (i.e. suspended, see Figure 10, wait period 108 asserted and de-asserted when chip enable 101 is at a logical low level); Paragraph 0084, Following a latency period (see WAIT signal 108), the synchronous burst mode read operation resumes (see CLK signal 106, CE# signal 101), and wherein the second signal line is used to trigger the data transfer (Fig. 11, Chip enable (CE) pin is used to perform a data burst access; Paragraph 0068, when a flash memory is operated in Synchronous Burst access, data read from the memory array may be output in bursts synchronized with the clock signal 76 on the clock [CLK] pin. To start the read cycle, the CE# signal 71 may be asserted to enable read operations).
Chae and Redaelli are analogous art because they are in the same field of endeavor of controlling data transfer via a communication bus between memory controllers and memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae/Thakkar’s method to incorporate the teachings of Redaelli and enable the data burst to be triggered based on a chip enable signal.
One of ordinary skill in the art would be motivated to make the modifications in order to increase flexibility in providing a high-speed connection to a memory while increasing read performance (See Redaelli: Paragraph 0018).
Regarding claim 10, the combination of Chae/Thakkar/Redaelli teaches the method of claim 9.
Redaelli teaches the method comprising wherein the second signal line corresponds to one of: a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin (Fig. 11, Chip enable (CE) pin is used to perform a data burst access; Paragraph 0068, when a flash memory is operated in Synchronous Burst access, data read from the memory array may be output in bursts synchronized with the clock signal 76 on the clock [CLK] pin. To start the read cycle, the CE# signal 71 may be asserted to enable read operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae/Thakkar’s method to incorporate the teachings of Redaelli and enable the data burst to be triggered based on a chip enable signal.
One of ordinary skill in the art would be motivated to make the modifications in order to increase flexibility in providing a high-speed connection to a memory while increasing read performance (See Redaelli: Paragraph 0018).
Regarding claim 16, Chae in view of Thakkar teaches the non-transitory computer-readable storage medium of claim 15. Neither Chae nor Thakkar teaches the non-transitory computer-readable storage medium comprising wherein the operations further comprise maintaining a second signal line operatively coupled with the processing logic at a logical level throughout the data transfer being active and suspended, and wherein the second signal line is used to trigger the data transfer.
Redaelli teaches the non-transitory computer-readable storage medium comprising wherein the operations further comprise maintaining a second signal line operatively coupled with the processing logic at a logical level throughout the data transfer being active and suspended (Fig. 11, Chip enable signal line operates at a logic level when data transfer is active or waiting (i.e. suspended, see Figure 10, wait period 108 asserted and de-asserted when chip enable 101 is at a logical low level); Paragraph 0084, Following a latency period (see WAIT signal 108), the synchronous burst mode read operation resumes (see CLK signal 106, CE# signal 101), and wherein the second signal line is used to trigger the data transfer (Fig. 11, Chip enable (CE) pin is used to perform a data burst access; Paragraph 0068, when a flash memory is operated in Synchronous Burst access, data read from the memory array may be output in bursts synchronized with the clock signal 76 on the clock [CLK] pin. To start the read cycle, the CE# signal 71 may be asserted to enable read operations).
Chae and Redaelli are analogous art because they are in the same field of endeavor of controlling data transfer via a communication bus between memory controllers and memory devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae/Thakkar’s non-transitory computer-readable storage medium to incorporate the teachings of Redaelli and enable the data burst to be triggered based on a chip enable signal.
One of ordinary skill in the art would be motivated to make the modifications in order to increase flexibility in providing a high-speed connection to a memory while increasing read performance (See Redaelli: Paragraph 0018).
Regarding claim 17, the combination of Chae/Thakkar/Redaelli teaches the non-transitory computer-readable storage medium of claim 16.
Redaelli teaches the non-transitory computer-readable storage medium comprising wherein the second pin is one of a Chip Enable pin, an Address Latch Enable pin, or a Command Latch Enable pin (Fig. 11, Chip enable (CE) pin is used to perform a data burst access; Paragraph 0068, when a flash memory is operated in Synchronous Burst access, data read from the memory array may be output in bursts synchronized with the clock signal 76 on the clock [CLK] pin. To start the read cycle, the CE# signal 71 may be asserted to enable read operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chae/Thakkar’s non-transitory computer-readable storage medium to incorporate the teachings of Redaelli and enable the data burst to be triggered based on a chip enable signal.
One of ordinary skill in the art would be motivated to make the modifications in order to increase flexibility in providing a high-speed connection to a memory while increasing read performance (See Redaelli: Paragraph 0018).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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