DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zheng et al. (USP 10,814,726).
For claim 1, Zeng teaches a drive circuit (Figure 7), wherein the drive circuit comprises a driver module (24), a delay module (111, 121, 122, 141, 142, 112, 131, 132) and a control module (10); a first output terminal of the control module (L1) is connected to a first controlled terminal of the delay module (L1), a second output terminal of the control module (D1) is connected to a second controlled terminal of the delay module (D1) , a third output terminal of the control module (S2) is connected to a control terminal of the driver module (24 via 143 and 132), and an output terminal of the delay module (CON) is connected to the control terminal of the driver module (24); the control module is configured to: after detecting a switch-on signal (reset signal to microcontroller is in inactive state), output a drive signal of a second level to the driver module (CON is at high level), so as to control the driver module to be switched on; and after detecting a switch-off signal (reset signal to microcontroller is in active state), output a drive signal of a fourth level to the driver module, so as to control the driver module to be switched off (CON is at low level); the delay module is configured to output a delay signal of preset duration to the driver module according to detection of an edge signal at the second controlled terminal in a case that the control module is being reset (paragraphs [0052]-[0055]); and the driver module is configured to: according to the delay signal of preset duration, maintain a first state within the preset duration, the first state being the same as a second state (CON is at a high level until the end of the preset duration, [0052]-[0055]) ; wherein the second state is a working state of the driver module before the control module is reset, and the second state comprises being on or off (on, as understood by examination of Figure 2 and [0052]-[0055)) as called for in claim 1.
For claim 2, wherein the delay module comprises a delay unit (111, 121, 122, 141, 142, 112, 131, 132) and a first pull- up unit (R9); a first controlled terminal of the delay unit (L1) is connected to both the first pull-up unit (R9) and a first output terminal of the control module (via R10), a second controlled terminal of the delay unit (D1) is connected to a second output terminal of the control module (D1), and an output terminal of the delay unit (CON) is connected to a control terminal of the driver module (gate of 24, as understood by the examination of Figure 7); and the delay unit is configured to: a. when an electrical signal of a first level is detected at the first controlled terminal (when L2 is high, [0069]) and an edge signal (falling edge of D2) is detected at the second controlled terminal (D3 is based on 122 being triggered, [0069]), output a delay signal of a second level (CON is high, i.e., 23 is conducting, [0069]); and b. when an electrical signal of a third level is detected at the first controlled terminal (when H2 is low, [0059]), output a delay signal of a fourth level (CON is low, i.e., 23 is disconnected, [0059]); c. wherein the fourth level is a reverse level of the second level, the third level is a reverse level of the first level, and the low-side driver module is switched when receiving an electrical signal of the second level and switched off when receiving an electrical signal of the fourth level.
For claim 5, Zeng further teaches: the control module is configured to: after detecting a switch-on signal (reset signal to microcontroller is inactive), output a control signal of the first level or the third level to the first controlled terminal of the delay module (H1 is low), and output a control signal of a fifth level or a first pulse width modulation PWM control signal to the second controlled terminal of the delay module (D3, [0046]-[0067]); and after detecting a switch-off signal (reset signal to microcontroller is active), output a control signal of the third level to the first controlled terminal and the second controlled terminal of the delay module ([0046]-[0067]), wherein a period of the first pulse width modulation PWM control signal is less than the preset duration ([0006]); and when the edge signal is a rising edge signal, the fifth level is a low level, or when the edge signal is a falling edge signal, the fifth level is a high level ([0046]-[0067]).
For claim 9, Zeng further teaches: wherein the drive circuit is configured to drive a load (21, Figures 2 and 5), and the load is grounded through the driver module (as understood by examination of Figures 2 and 5); and the control module is further configured to: at the end of the reset, output the drive signal based on a recheck signal input by a recheck module (141, Figure 5) or load state data stored in a storage module (S1), to control the high-side driver module (as understood by examination of Figure 5), wherein an input terminal of the recheck module is connected to a joint between the high-side driver module and the load module or connected to the control terminal of the high-side driver module (via the feedback signal to 10), and an output terminal of the recheck module is connected to the control module (via 131).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zeng (USP 10,814,726) in view of Jain et al. (US 2011/0193588).
Regarding claim 3, Zeng’s figure 5 shows a drive circuit comprising all the aspects of the present invention as noted above except the details of the delay module comprising a second pull up unit as called for in claim 3.
Jain et al.’s figure 1 shows a detailed structure of a delay module comprising cascaded delay units. Each delay unit include a pull up unit (p transistor). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to implement Zeng’s 122 using a plurality of series-connected CMOS inverters since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
The modified version of Zeng as defined above teaches that the delay module further comprises a second pull-up unit (pull-up portion of the last inverter within the plurality of series-connected inverters), and the second pull-up unit is connected to the second controlled terminal of the delay unit (when the last inverter outputs a high signal, the second pull-up unit will inherently connect the positive power supply to the second controlled terminal).
For claim 4, the modified version of Zeng teaches that the delay unit comprises N cascaded delay components (series-connected inverters, as defined above); and first input terminals of the delay components are mutually connected (power supply terminals mutually connected to a positive power supply), wherein a joint serves as the first controlled terminal of the delay unit (interconnection between R1 and R2, as understood by examination of Figure 5), a second input terminal of a 1st delay component (control terminal of leftmost inverter within the series-connected inverters) is connected to the second controlled terminal of the delay unit (as understood by examination of Figure 2), a second input terminal of an (i+1)th delay component is connected to an output terminal of an ith delay component (inherent of series-connected inverters), and an output terminal of an Nth delay component serves as the output terminal of the delay unit, wherein 1<=i<=N and N is an integer greater than 1.
Allowable Subject Matter
Claims 6-8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2843 4/8/2026