DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 12 is objected to because of the following informalities: Line 3 recites “a memory manger module” which contains a misspelling and should be --a memory manager module--. Line 5 recites “a cache configured to manages” which contains a misspelling and should be --a cache configured to manage--. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claim 1 recites “memory module configured to…perform…”
Claims 2-19 either indirectly or directly recites a means-for limitation involving the previously recited memory module, thus, is also interpreted under 35 USC 112(f)
Claim 7 recites “a memory tiering module configured to… receive…track… classify…”
Claims 8-12 either indirectly or directly recites a means-for limitation involving the previously recited memory tiering module, thus, is also interpreted under 35 USC 112(f)
Claim 12 recites “a page tracking module configured to track…,” “a memory manger module configured to control…,” “an input/output (IO) scheduling module configured to perform…” and “a memory to IO (M2I) mapping module configured to manage…”
Claim 20 recites “a method of inter/intra-memory tiering by a memory module…”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. For example:
Regarding “memory module configured to…perform…,” the structure of the memory module is a combination of software, firmware, and/or hardware, page 5, lines 20-22
Regarding “a memory tiering module configured to… receive…track… classify…,” resides on the memory module according to Page 11, Lines 3-4 of which its structure a combination of software, firmware, and/or hardware, page 5, lines 20-22
Regarding “a page tracking module configured to track…,” “a memory manger module configured to control…,” “an input/output (IO) scheduling module configured to perform…” and “a memory to IO (M2I) mapping module configured to manage…” is included on the memory tiering module according to Page 11, Lines 20-24, thus, its structure is also comprised of a combination of software, firmware, and/or hardware, page 5, lines 20-22
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-4, 7-8, 10 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the terms “hot” and “warm” in are a relative terms which renders the claim indefinite. The terms “hot” and “warm” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In other words, the specification fails to provide the metes and bounds for determining a “hot” page from a “warm” page, as a page that is considered by one memory system to be “warm” could also be considered by a different memory system to be “hot”. It is noted that while the specification indicates that an access frequency could be used to determine a hot page if it is greater than a hot frequency threshold (see Page 8, Lines 18-21), the specification fails to provide examples of said hot frequency threshold. For the purposes of examination, it shall be interpreted that a page being migrated to a faster memory meets the threshold for being considered a warm page.
Claims 3-4, 7 and 10 also recites the term “warm” and is rejected under 35 USC 112(b) for the same reasons as claim 2, as outlined above.
Regarding claim 3, the terms “cold” and “warm” in are a relative terms which renders the claim indefinite. The terms “cold” and “warm” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In other words, the specification fails to provide the metes and bounds for distinguishing between a “cold” page from a “warm” page, as a page that is considered by one memory system to be “warm” could also be considered by a different memory system to be “cold”. For the purposes of examination, it shall be interpreted that a page being migrated to a faster memory meets the threshold for being considered a warm page.
Regarding claim 8, the claim recites “wherein the memory tiering module is further configured to, if the memory page is classified as hot, report the hot page to the host CPU,” of which there is lack of antecedent basis for “the host CPU” which renders the claim indefinite. It is unclear as to whether Applicants intended for this to be the embedded CPU, or a host CPU (i.e., an entirely new CPU). For the purposes of examination, the claim shall be interpreted as the former.
Regarding claim 12, “an input/output (IO) scheduling module configured to perform endurance consideration” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. In this instance, one/the corresponding structure refers to computer implemented means-plus function. The written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Performing endurance consideration is a specialized computer function that would require an algorithm to be disclosed, in addition to the physical structure that would perform the algorithm. The specification does not provide sufficient details such that one of ordinary skill in the art would understand the algorithm that is used to perform endurance consideration. It is noted that while the specification indicates write regulation and page elimination are examples of endurance consideration techniques, the specification is silent with regards to the algorithm in which these techniques would be performed. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. For the purposes of examination, Examiner is interpreting the limitation to refer to any known processor performing endurance consideration.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Regarding claim 12, “an input/output (IO) scheduling module configured to perform endurance consideration” as described supra, does not provide adequate structure to perform the claimed function of performing endurance consideration. Therefore, the specification does not appear to provide sufficient detail such that one of ordinary skill can reasonably conclude that the inventor had possession of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-12, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mahajan et al. (US 2020/0356300 A1) hereinafter Mahajan et al. in view of Hoang et al. (US 2024/0070065 A1) hereinafter Hoang et al.
Regarding claim 1, Mahajan et al. teaches a system for perform inter/intra-memory tiering, the system comprising:
a tier 1 memory (in-memory cache 136 Paragraph [0028], [0041]); and
memory module (comprised of storage controller 900 with downloaded processor-executable instructions to perform the methods Paragraph [0072]) comprising a tier 2 memory and a tier 3 memory (including the HDD tier 102 and SSD tier 124 Paragraph [0028]), wherein the memory module is configured to:
perform inter-memory tiering between the tier 1 memory and the memory module (read-accessed grains are migrated from hot extents in the HDD tier 102 to in-memory cache Paragraph [0040]), and
perform intra-memory tiering between the tier 2 memory and the tier 3 memory (write-accessed grains are migrated from hot extents in the HDD tier 102 to SSD tier Paragraph [0040]).
Mahajan et al. does not appear to explicitly teach, however, Hoang et al. teaches a host central processing unit (CPU) (host processor 110 contains one or more CPU cores 111 Paragraph [0011], also see Fig. 1).
The disclosures of Mahajan et al. and Hoang et al., hereinafter MH, are analogous art to the claimed invention because they are in the same field of endeavor of memory tiering and/or migrating data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of MH before them, to modify the teachings of Mahajan et al. to include the teachings of Hoang et al. since both MH teach moving data across different memory tiers. Therefore it is applying a known technique (including a host processor to perform certain functions Paragraph [0011] of Hoang et al.) to a known device (memory system performing tiering across an in-memory cache and SSD/HDD tiers Paragraphs [0028], [0040] of Mahajan et al.) ready for improvement to yield predictable results (selected functions are performed by the host processor [0011] of Hoang et al.), KSR, MPEP 2143.
Regarding claim 2, MH teaches all of the features with respect to claim 1 as outlined above.
Mahajan et al. further teaches wherein the inter-memory tiering between the tier 1 memory and the memory module comprises at least one of: hot page promotion from the memory module to the tier 1 memory, or warm page demotion from the tier 1 memory to the memory module (read-accessed grains are migrated from hot extents in the HDD tier 102 to in-memory cache Paragraph [0040]).
Regarding claim 3, MH teaches all of the features with respect to claim 1 as outlined above.
Mahajan et al. further teaches wherein the intra-memory tiering between the tier 2 memory and the tier 3 memory comprises at least one of: warm page promotion from the tier 3 memory to the tier 2 memory, and cold page demotion from the tier 2 memory to the tier 3 memory (write-accessed grains are migrated from hot extents in the HDD tier 102 to SSD tier Paragraph [0040]).
Regarding claim 7, MH teaches all of the features with respect to claim 1 as outlined above.
Hoang et al. further teaches wherein the memory module further comprises: an embedded CPU (information handling system includes a central processing unit (CPU) Paragraph [0017]); and a memory tiering module (tiering manager 250) configured to: receive, from the embedded CPU, an intra-memory tiering configuration (the decision to move data within a tiered memory architecture will typically involve the execution of code by CPU 210 Paragraph [0019]), track page meta of a memory page based on the intra-memory tiering configuration (tiering manager monitors accesses to the page of data and determines whether it should be moved from slow memory device to hot memory device Paragraph [0019]), and classify the memory page as one of hot, warm, or cold based on the tracked paged meta (for example, when a number of accesses has exceeded a particular rate (i.e., the page is hot), then Page A should be moved to fast memory Paragraph [0019]).
Regarding claim 8, MH teaches all of the features with respect to claim 7 as outlined above.
Hoang et al. further teaches wherein the memory tiering module is further configured to, if the memory page is classified as hot, report the hot page to the host CPU (once it has been determined that the page of data (Page A) has exceeded a particular rate of access, tiering manager initiates a move of the memory page by using the CPU to read and write the data Paragraphs [0019]-[0020]).
Regarding claim 9, MH teaches all of the features with respect to claim 1 as outlined above.
Mahajan et al. further teaches wherein the page meta comprises at least one of access frequency or recency (extents can be classified as hot or cold extents based on numbers of I/O operations associated with various grains in respective extents Paragraph [0053]).
Regarding claim 10, MH teaches all of the features with respect to claim 7 as outlined above.
Mahajan et al. further teaches wherein the memory tiering module is further configured to, if the memory page is classified as warm, move the memory page from the from the tier 3 memory to the tier 2 memory (write-accessed grains are migrated from hot extents in the HDD tier 102 to SSD tier Paragraph [0040]).
Regarding claim 11, MH teaches all of the features with respect to claim 7 as outlined above.
Mahajan et al. further teaches wherein the memory tiering module is further configured to, if the memory page is classified as cold, move the memory page from the from the tier 2 memory to the tier 3 memory (an extent identified as a cold extent is demoted from an SSD tier to a lower tier (e.g., an HDD tier, a tape drive, etc.) Paragraph [0064]).
Regarding claim 12, MH teaches all of the features with respect to claim 7 as outlined above.
Hoang et al. further teaches wherein the memory tiering module comprises: a page tracking module configured to track the page meta of the memory page (tiering manager 350 monitors the access rates for particular pages of memory stored on the memory tiers Paragraph [0024]); a memory manger module configured to control page migration between the tier 2 memory and the tier 3 memory (CXL memory module operates to determine when a page of data is more or less commonly accessed and perform the actual movement of the page of data Paragraph [0025], for example, moving it from a lower, slower tier to a higher, faster tier Paragraph [0024]); a cache configured to manages data located to the tier 2 memory (CPU memory 420 uses a page table to manage stored data Paragraphs [0019]-[0021]); and a memory to IO (M2I) mapping module configured to manage mapping between memory and solid state device (SSD) addresses (CXL memory controller performs the mapping and remapping of the pages of data Paragraph [0025]). Mahajan et al. further teaches an input/output (IO) scheduling module configured to perform endurance consideration (the CXL memory controller utilizes a protocol that allows processors to access memory utilizing load/stored-based commands Paragraph [0014]).
Regarding claim 16, MH teaches all of the features with respect to claim 1 as outlined above.
Hoang et al. further teaches wherein the memory module comprises a compute express link (CXL) memory module (CMM) (tiering manager 300 is instantiated on, or incorporated into CXL memory controller 320 and CXL memory module 320 Paragraph [0025]).
Regarding claim 18, MH teaches all of the features with respect to claim 1 as outlined above.
Hoang et al. further teaches wherein the tier 1 memory comprises dynamic random access memory (DRAM) (in the host environment, processor 402 includes memories 420, 425 which are dynamic RAM (DRAM) Paragraph [0037]).
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over MH in further view of Bruce et al. (US 2020/0151098 A1) hereinafter Bruce et al.
Regarding claim 13, MH teaches all of the features with respect to claim 1 as outlined above.
MH does not appear to explicitly teach, however, Bruce et al. teaches wherein the memory module further comprises a tier 1 candidate memory (the storage controller further includes an internal SRAM which is a high speed read buffer Paragraph [0203]).
The disclosures of MH and Bruce et al., hereinafter MHB, are analogous art to the claimed invention because they are in the same field of endeavor of memory tiering and/or migrating data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of MHB before them, to modify the teachings of MH to include the teachings of Bruce et al. since both MHB teach moving data across different memory tiers. Therefore it is applying a known technique (including a high speed SRAM buffer to move data [0203] of Bruce et al.) to a known device (memory system performing tiering across an in-memory cache and SSD/HDD tiers Paragraphs [0028], [0040] of Mahajan et al.) ready for improvement to yield predictable results (an internal SRAM is used as a high speed read buffer to move data [0203] of Bruce et al.), KSR, MPEP 2143.
Regarding claim 14, MHB teaches all of the features with respect to claim 13 as outlined above.
Mahajan et al. further teaches wherein the memory module is further configured to: remove a memory page identified as hot from the tier 2 memory or the tier 3 memory, and the memory page… being hot promoted to the tier 1 memory (read-accessed grains are migrated from hot extents in the HDD tier 102 to in-memory cache Paragraph [0040]) and Bruce et al. further teaches to temporarily store the memory page in the tier 1 candidate memory prior to being hot promoted (the internal SRAM 114 can be used as a high-speed buffer for moving data from flash/drives to the host Paragraph [0203]).
Regarding claim 15, MHB teaches all of the features with respect to claim 13 as outlined above.
Bruce et al. further teaches wherein the tier 1 candidate memory comprises static random access memory (SRAM) (an internal SRAM which is a high speed read buffer Paragraph [0203]).
Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over MH in further view of Kodama (US 2022/0261268 A1) hereinafter Kodama.
Regarding claim 17, MH teaches all of the features with respect to claim 1 as outlined above.
MH does not appear to explicitly teach, however, Kodama further teaches wherein the tier 3 memory comprises NAND flash memory (a level LV2 includes a NAND flash memory Paragraph [0034]).
The disclosures of MH and Kodama, hereinafter MHK, are analogous art to the claimed invention because they are in the same field of memory tiering and/or data migration in a memory system. Because MHK teach the use of utilizing different memories for different tiers (ex. SSD as one tier and HDD as another tier), it would have been obvious to one skilled in the art to substitute one type of memory for another to achieve the predictable result of availability of data stored in the particular type of memory as disclosed by Kodama, in this case, NAND flash memory (KSR, MPEP 2143).
Regarding claim 19, MH teaches all of the features with respect to claim 1 as outlined above.
MH does not appear to explicitly teach, however, Kodama further teaches wherein the tier 2 memory comprises dynamic random access memory (DRAM) (a level LV1 includes a DRAM Paragraph [0034]).
The disclosures of MH and Kodama, hereinafter MHK, are analogous art to the claimed invention because they are in the same field of memory tiering and/or data migration in a memory system. Because MHK teach the use of utilizing different memories for different tiers (ex. SSD as one tier and HDD as another tier), it would have been obvious to one skilled in the art to substitute one type of memory for another to achieve the predictable result of availability of data stored in the particular type of memory as disclosed by Kodama, in this case, DRAM (KSR, MPEP 2143).
Allowable Subject Matter
Claims 4-6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Specifically regarding claim 4, “wherein the memory module further comprises a memory tiering module configured to: receive, from the host CPU, an inter-memory tiering configuration, track page meta of a memory page based on the inter-memory tiering configuration, and classify the memory page as one of hot or warm based on the tracked paged meta,” tracking and classifying memory pages based on an inter-memory tiering configuration sent by a host CPU is not taught by the prior art of record. The closest prior art of record is Hoang et al. which teaches utilizing a tiering manager to offload tiering decisions to the memory device. While the host CPU still aids in the transferring of data across tiers, Hoang et al., in combination with Mahajan et al. still teaches away from the claim, as the tiering manager is responsible for the tracking and classifying and thus, never receives any inter-memory tiering configuration from the host CPU. Claims 5-6 would be allowable at least due to its dependency on claim 4.
Claim 20 is allowed.
Specifically regarding claim 20, “A method of inter/intra-memory tiering by a memory module, the method comprising: receiving, from a host central processing unit (CPU), a first configuration for inter-memory tiering between a tier 1 memory and the memory module; receiving, from a CPU included in the memory module, a second configuration for intra-memory tiering between a tier 2 memory and a tier 3 memory, the tier 2 memory and the tier 3 memory being included in the memory module; tracking page meta of a memory page; and performing, for the memory page, one of inter-memory tiering between the tier 1 memory and the memory module, or intra-memory tiering between the tier 2 memory and the tier 3 memory, based on the first configuration or the second configuration, respectively, and the tracked page meta,” is not taught by the prior art of record. The closest prior art of record is Hoang et al. which teaches utilizing a tiering manager to offload tiering decisions to the memory device. While the host CPU still aids in the transferring of data across tiers, Hoang et al., in combination with Mahajan et al. still teaches away from the claim, as the tiering manager is responsible for the tracking and classifying and thus, never receives any inter-memory tiering configuration from the host CPU. In other words, as similarly recited in claim 1, the prior art does not distinguish between utilizing a host CPU and memory module CPU for performing different levels of tiering.
While one or more reasons are offered above citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Hoang et al. and Mahajan et al., when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Conclusion
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139