DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko (US 5,955,912).
Claim 1, Liu discloses an integrated circuit (Fig. 3) device, comprising:
a plurality of selecting modules (A first 2-to-1 multiplexer consists of transmission gates 211 and 212 and inverter 241; A second 2-to-1 multiplexer consists of transmission gates 213 and 214 and inverter 242, see col. 1, line 55 to col. 2, line 28), wherein each of the plurality of selecting modules is configured to receive a first input signal (I1, Fig. 3), a second input signal (I3), a first selecting signal (S0) and a second selecting signal (output from inverter 201), and select the first input signal or the second input signal to generate an output signal (output of inverter 241) according to a first selecting signal and a second selecting signal; and a selecting signal providing module (inverter 201), configured to provide the first selecting signal and the second selecting signal.
Claim 2, Liu discloses the integrated circuit device as claimed in claim 1, wherein the first selecting signal and the second selecting signal are inverted (see inverter 201).
Claim 3, Liu discloses the integrated circuit device as claimed in claim 1, wherein the selecting signal providing module comprises: an inverter (inverter 201, Fig. 3), having an input terminal and an output terminal, wherein the input terminal of the inverter receives the first selecting signal, and the output terminal of the inverter outputs the second selecting signal.
Claim 4, Liu discloses the integrated circuit device as claimed in claim 1, wherein each of the plurality of selecting modules comprises a multiplexer (A first 2-to-1 multiplexer consists of transmission gates 211 and 212 and inverter 241; A second 2-to-1 multiplexer consists of transmission gates 213 and 214 and inverter 242, see col. 1, line 55 to col. 2, line 28).
Claim(s) 1, 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sigal et al. (US 5,543,731).
Claim 1, Sigal discloses an integrated circuit device (Fig. 6), comprising:
a plurality of selecting modules (plurality of GATE1, Fig. 6), wherein each of the plurality of selecting modules is configured to receive a first input signal (DATA_A OR DATA_B), a second input signal (DATA_A OR DATA_B), a first selecting signal and a second selecting signal (SELECT_A, SELECT_B), and select the first input signal or the second input signal to generate an output signal (output A) according to a first selecting signal and a second selecting signal; and a selecting signal providing module (inherent element for output the selecting signal, SELECT_A, SELECT_B), configured to provide the first selecting signal and the second selecting signal.
Claim 4, Sigal discloses integrated circuit device as claimed in claim 1, wherein each of the plurality of selecting modules comprises a multiplexer (MULTIPLEXOR, Fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sigal et al. (5,543,731).
Claim 6, Sigal discloses the integrated circuit device (see redrawn of Fig. 6 below) as claimed in claim 1, wherein each of the plurality of selecting modules comprises:
a first transistor (transistor T1), having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor receives a first reference voltage (Vdd), and the control terminal of the first transistor receives the second selecting signal (SELECT_B);
a second transistor (transistor T2), having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor receives the first reference voltage (Vdd), the second terminal of the second transistor is coupled to the second terminal of the first transistor, and the control terminal of the second transistor receives the first input signal (DATA_B);
a third transistor (transistor T3), having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor, and the control terminal of the third transistor receives the first selecting signal (SELECT_A);
a fourth transistor (transistor T4), having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth transistor is coupled to the first terminal of the third transistor, the second terminal of the fourth transistor is coupled to the second terminal of the third transistor, and the control terminal of the fourth transistor receives the second input signal (DATA_A);
a fifth transistor (transistor T5), having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fifth transistor is coupled to the second terminal of the third transistor, and the control terminal of the fifth transistor receives the first selecting signal (SELECT_1);
a sixth transistor (transistor T6), having a first terminal, a second terminal and a control terminal, wherein the second terminal of the sixth transistor is coupled to the second terminal of fifth transistor, and the control terminal of the sixth transistor receives the second selecting signa (SELECT_B);
a seventh transistor (transistor T7), having a first terminal, a second terminal and a control terminal, wherein the first terminal of the seventh transistor receives the second reference voltage (ground through N-type transistor connected to CLOCK signal), the second terminal of the seventh transistor is coupled to the first terminal of the fifth transistor, and the control terminal of the seventh transistor receives the SECOND input signal (DATA_2);
an eighth transistor (transistor T8), having a first terminal, a second terminal and a control terminal, wherein the first terminal of the eighth transistor receives the second reference voltage (ground through N-type transistor connected to CLOCK signal), the second terminal of the eighth transistor is coupled to the first terminal of the sixth transistor, and the control terminal of the eighth transistor receives the FIRST input signal (DATA_B);
Thus, Sigal discloses the invention substantially as claimed, but does not disclose the seventh transistor receives the first input signal, the eighth transistor receives the second input signal, and a ninth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the ninth transistor receives the first reference voltage, the second terminal of the ninth transistor generates the first output signal, and the control terminal of the ninth transistor is coupled to the second terminal of the third transistor; and a tenth transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal of the tenth transistor receives the second reference voltage, the second terminal of the tenth transistor is coupled to the second terminal of the ninth transistor, and the control terminal of the tenth transistor is coupled to the control terminal of the ninth transistor.
In the same field of endeavor, Fig. 4 of Sigal shows a multiplexer (transistors N3-N8 and P3-P6, and P8) including an output inverter 13 with a ninth transistor (P7) and a tenth transistor (N7).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to provide an output inverter with a ninth transistor (P7) and a tenth transistor (N7) connected between the GATE1 and NAND1 of Fig. 6, in order to inverse and amplify an output signal of the selecting module.
Furthermore, It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention was made to provide the seventh transistor with the first input signal, the eighth transistor with the second input signal, since it has been held that rearranging parts of an invention involves only routine skill in the art.
Claim 7, Sigal discloses the integrated circuit device as claimed in claim 6, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor and the ninth transistor is a P-type transistor (transistors T1-T4 and the ninth transistor are P-type transistor, see Figs. 4 and 6), and each of the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the tenth transistor is an N-type transistor (transistors T5-T8 and the tenth transistor are N-type transistor, see Figs. 4 and 6).
PNG
media_image1.png
478
745
media_image1.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (US 2020/0395938), Mizuno (US 2003/0201798) and Campbell (US 2005/0225359) disclose an integrated circuit device, comprising: a plurality of selecting modules, wherein each of the plurality of selecting modules is configured to receive a first input signal, a second input signal, a first selecting signal and a second selecting signal, and select the first input signal or the second input signal to generate an output signal according to a first selecting signal and a second selecting signal; and a selecting signal providing module, configured to provide the first selecting signal and the second selecting signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH Q TRAN/Primary Examiner, Art Unit 2845 6/2/26
Prosecution Insights