DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 11/19/2024 are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20250006252 A1) in view of Kasai et al. (US 20220291845 A1), hereinafter referred as Kasai in further view of Ojalvo et al. (US 20150355858 A1) hereinafter referred as Ojalvo.
As per claim 1, Yang substantially teaches an operating method of a storage device including a nonvolatile memory device and a storage controller, the operating method (According to various embodiments, the data storage device 100 may comprise a controller such as a memory controller 110 and may further comprise a non-volatile (NV) memory 120. The NV memory 120 is configured to store data and information; Yang p. 0018) comprising:
transmitting, by the storage controller, a program command and write data to the nonvolatile memory device (at step 310, write data DAT to be written by the host device 50 is read from the buffer 113 and written into the page buffer 121 of the NV memory 120. At step 320, the write data DAT is encoded to generate corresponding check data PTY. Accordingly, the generated check data PTY is written into the page buffer…If the detection result of step 340 is no, the flow proceeds to step 350, where the memory controller 110 will issue a program command to the control circuit 123 of the NV memory 120, such that the control circuit 123 will program the write data DAT and check data PTY in the page buffer 121 to one or more pages of the NV memory element 122_k; Yang p. 0028);
performing, by the nonvolatile memory device, an error detection operation on the write data in a page buffer circuit based on the error detection activation information (At step 330, while generating the check data PTY, the verification circuit 150 is employed to verify (i.e., on-the-fly verification) the write data DAT and the check data PTY, thereby generating an error detection result. In one embodiment, the verification circuit 150 may include another encoder similar to the encoder 130….After writing of the write data DAT into the page buffer 121 is completed, the encoder 130 begins to encode the write data DAT to generate check data PTY. Once the encoder 130 starts to output the check data PTY bit by bit, the verification circuit 150 will immediately (on-the-fly) perform error detection on the write data DAT and generated portion (e.g. partial bits) of check data PTY. If an error is detected, as shown by the timing illustrated by FIG. 6, the write data DAT will be written into the page buffer 121 again (overwriting the previous write), the write data DAT will be encoded again, and the re-generated portion of check data PTY will be verified again; Yang p. 0028-0029);
and programming, by the nonvolatile memory device, the write data to memory cells in the nonvolatile memory device based on an error not being detected in the write data (Until no errors are found (i.e., repeating steps 310-340), the write operation of the write data DAT is considered completed. If the detection result of step 340 is no, the flow proceeds to step 350, where the memory controller 110 will issue a program command to the control circuit 123 of the NV memory 120, such that the control circuit 123 will program the write data DAT and check data PTY in the page buffer 121 to one or more pages of the NV memory element 122_k. As a result, the flow ends. In this embodiment, before the encoded data passes verification, it is only written into the page buffer 121, but not programmed to the NV memory element 122_k; Yang p. 0028).
Yang does not explicitly teach transmitting, by the storage controller, error detection activation information to the nonvolatile memory device.
However, Kasai in an analogous art teaches transmitting, by the storage controller, error detection activation information to the nonvolatile memory device (The setting registers 190 may be accessed from the outside, and the user can rewrite the selection information set (equates “error detection activation information” as it is stored in the setting register that tells the controller with the ECC to activate) in the setting register 190 by using a predetermined command. After receiving the write command of the setting register from the host computer through the input-output circuit 120 and writing the data, the controller 150 writes the write data to the setting register…The controller 150 includes a microcontroller or a state machine, and controls overall operations of the flash memory 100, such as reading, programming, erasing, and switching between different error detection and correction functions, according to commands or control signals received from outside.; Kasai p. 0025-0026).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang with the teachings of Kasai by configuring the storage controller to transmit error detection activation information (“selection information set”).
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ transmitting error detection activation information to the device in the system of Yang because Kasai teaches a setting step, setting selection information to select a first error detection and correction function so the error detection and correction capability also increases, suppressing the decrease in reliability (Kasai p. 0025).
Yang in view of Kasai, as combined above, does not explicitly teach transmitting, by the nonvolatile memory device, the write data as error data to the storage controller based on an error being detected in the write data.
However, Ojalvo in an analogous art teaches transmitting, by the nonvolatile memory device, the write data as error data to the storage controller based on an error being detected in the write data (the SSD controller accepts data for storage from a host computer and stores at least part of the data in a volatile buffer of the Flash device, which then writes or programs the buffered data to analog memory cells of the Flash device. Occasionally, the programming operation fails, and the original buffered data needs to be recovered and re-programmed…the disclosed methods enable data recovery from programming failure, using both the page buffer and the non-volatile memory. The disclosed techniques do not rely on the availability of the original data in the SSD controller and/or the host; Ojalvo p. 0015, 0017, 0021).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai, as combined, with the teachings of Ojalvo by configuring the memory device to transmit the write data as error data to the storage controller based on an error being detected.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ transmitting the write data based on an error being detected in the system of Yang in view of Kasai because Ojalvo teaches storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data to recover from programming failure (Ojalvo p. 0021).
As per claim 13, Yang substantially teaches an operating method of a nonvolatile memory device, the operating method (According to various embodiments, the data storage device 100 may comprise a controller such as a memory controller 110 and may further comprise a non-volatile (NV) memory 120. The NV memory 120 is configured to store data and information; Yang p. 0018) comprising:
receiving a program command and write data from the storage controller (at step 310, write data DAT to be written by the host device 50 is read from the buffer 113 and written into the page buffer 121 of the NV memory 120. At step 320, the write data DAT is encoded to generate corresponding check data PTY. Accordingly, the generated check data PTY is written into the page buffer…If the detection result of step 340 is no, the flow proceeds to step 350, where the memory controller 110 will issue a program command to the control circuit 123 of the NV memory 120, such that the control circuit 123 will program the write data DAT and check data PTY in the page buffer 121 to one or more pages of the NV memory element 122_k; Yang p. 0028);
performing, based on error detection activation information, an error detection operation by detecting whether a same pattern repeats in the write data of a page buffer circuit At step 330, while generating the check data PTY, the verification circuit 150 is employed to verify (i.e., on-the-fly verification) the write data DAT and the check data PTY, thereby generating an error detection result. In one embodiment, the verification circuit 150 may include another encoder similar to the encoder 130….After writing of the write data DAT into the page buffer 121 is completed, the encoder 130 begins to encode the write data DAT to generate check data PTY. Once the encoder 130 starts to output the check data PTY bit by bit, the verification circuit 150 will immediately (on-the-fly) perform error detection on the write data DAT and generated portion (e.g. partial bits) of check data PTY. If an error is detected, as shown by the timing illustrated by FIG. 6, the write data DAT will be written into the page buffer 121 again (overwriting the previous write), the write data DAT will be encoded again, and the re-generated portion of check data PTY will be verified again; Yang p. 0028-0029);
and based on an error being not detected in the write data, programming the write data to memory cells in nonvolatile memory device (Until no errors are found (i.e., repeating steps 310-340), the write operation of the write data DAT is considered completed. If the detection result of step 340 is no, the flow proceeds to step 350, where the memory controller 110 will issue a program command to the control circuit 123 of the NV memory 120, such that the control circuit 123 will program the write data DAT and check data PTY in the page buffer 121 to one or more pages of the NV memory element 122_k. As a result, the flow ends. In this embodiment, before the encoded data passes verification, it is only written into the page buffer 121, but not programmed to the NV memory element 122_k; Yang p. 0028).
Yang does not explicitly teach receiving error detection activation information from a storage controller.
However, Kasai in an analogous art teaches receiving error detection activation information from a storage controller (The setting registers 190 may be accessed from the outside, and the user can rewrite the selection information set (equates “error detection activation information” as it is stored in the setting register that tells the controller with the ECC to activate) in the setting register 190 by using a predetermined command. After receiving the write command of the setting register from the host computer through the input-output circuit 120 and writing the data, the controller 150 writes the write data to the setting register…The controller 150 includes a microcontroller or a state machine, and controls overall operations of the flash memory 100, such as reading, programming, erasing, and switching between different error detection and correction functions, according to commands or control signals received from outside; Kasai p. 0025-0026).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang with the teachings of Kasai by configuring the storage controller to transmit error detection activation information (“selection information set”).
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ transmitting error detection activation information to the device in the system of Yang because Kasai teaches a setting step, setting selection information to select a first error detection and correction function so the error detection and correction capability also increases, suppressing the decrease in reliability (Kasai p. 0025).
Yang in view of Kasai as combined above, does not teach based on an error being detected in the write data, transmitting the write data as error data to the storage controller.
However, Ojalvo teaches based on an error being detected in the write data, transmitting the write data as error data to the storage controller (the SSD controller accepts data for storage from a host computer and stores at least part of the data in a volatile buffer of the Flash device, which then writes or programs the buffered data to analog memory cells of the Flash device. Occasionally, the programming operation fails, and the original buffered data needs to be recovered and re-programmed…the disclosed methods enable data recovery from programming failure, using both the page buffer and the non-volatile memory. The disclosed techniques do not rely on the availability of the original data in the SSD controller and/or the host; Ojalvo p. 0015, 0017, 0021)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai, as combined, with the teachings of Ojalvo by configuring the memory device to transmit the write data as error data to the storage controller based on an error being detected.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ transmitting the write data based on an error being detected in the system of Yang in view of Kasai because Ojalvo teaches storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data to recover from programming failure (Ojalvo p. 0021).
As per claim 18, Yang teaches a nonvolatile memory device comprising:
perform, based on error detection activation information, an error detection operation by detecting whether a same pattern in the write data repeats before programming the write data to the memory cell array (an error check operation is performed on encoded data that is generated by a flash memory controller, thereby to determine whether to repeat data programming operations (Yang p. 0003). while generating the check data PTY, the verification circuit 150 is employed to verify (i.e., on-the-fly verification) the write data DAT and the check data PTY, thereby generating an error detection result (Yang p. 0028),
and based on an error being not detected in the write data, program the write data to the memory cells (Only after verification is passed, the encoded data is written into the NV memory element 122_k. Please refer to a flow chart shown in FIG. 4, as well as schematic diagram of partial architecture of the memory controller 110 and the NV memory 120 shown in FIG. 5. First, at step 310, write data DAT to be written by the host device 50 is read from the buffer 113 and written into the page buffer 121 of the NV memory 120. At step 320, the write data DAT is encoded to generate corresponding check data PTY. Accordingly, the generated check data PTY is written into the page buffer 121. At step 330, while generating the check data PTY, the verification circuit 150 is employed to verify (i.e., on-the-fly verification) the write data DAT and the check data PTY, thereby generating an error detection result; Yang p. 0028).
Yang does not explicitly teach a memory cell array comprising, a plurality of memory cells, an input/output circuit configured to receive write data from a storage controller.
However Kasai in an analogous art teaches a memory cell array comprising, a plurality of memory cells, an input/output circuit configured to receive write data from a storage controller (A flash memory 100 includes: a storage unit array 110, in which a plurality of storage units are disposed in a matrix; an input-output circuit connected to the external input-output terminal to output the read data to the outside or imports the data input from the outside…adapted to hold the data read from the selected page of the memory cell array; Kasai p. 0020);
a page buffer circuit connected to the memory cell array and configured to temporarily store the write data from the input/output circuit (a page buffer/sensing circuit 170, adapted to hold the data read from the selected page of the memory cell array 110, or hold the data to be programmed in the selected page; Kasai p. 0020);
and an error detection circuit configured to receive error detection activation information from the storage controller (a setting register for setting selection information for selecting the first error detection and correction function or the second error detection and correction function; and a controller, during a read operation or a write operation, to execute the first error detection and correction function or the second error detection and correction function based on the selection information; Kasai p. 0010)( an ECC circuit 130, adapted to perform generation of error correction codes for data to be programmed or error detection and correction; Kasai p. 0020),
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang with the teachings of Kasai by configuring the storage controller to transmit error detection activation information (“selection information set”).
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ transmitting error detection activation information to the device in the system of Yang because Kasai teaches a setting step, setting selection information to select a first error detection and correction function so the error detection and correction capability also increases, suppressing the decrease in reliability (Kasai p. 0025).
Yang in view of Kasai, as combined above, does not teach based on an error being detected in the write data, transmit the write data as error data to the storage controller.
However, Ojalvo in an analogous art teaches based on an error being detected in the write data, transmit the write data as error data to the storage controller (the SSD controller accepts data for storage from a host computer and stores at least part of the data in a volatile buffer of the Flash device, which then writes or programs the buffered data to analog memory cells of the Flash device. Occasionally, the programming operation fails, and the original buffered data needs to be recovered and re-programmed…the disclosed methods enable data recovery from programming failure, using both the page buffer and the non-volatile memory. The disclosed techniques do not rely on the availability of the original data in the SSD controller and/or the host; Ojalvo p. 0015, 0017, 0021),
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai, as combined, with the teachings of Ojalvo by configuring the memory device to transmit the write data as error data to the storage controller based on an error being detected.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ transmitting the write data based on an error being detected in the system of Yang in view of Kasai because Ojalvo teaches storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data to recover from programming failure (Ojalvo p. 0021).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of LEE et al. (US 20200226039 A1).
As per claim 2, Yang in view of Kasai in further view of Ojalvo teaches the operating method of claim 1.
Yang in view of Kasai in further view of Ojalvo, as combined, does not teach wherein the performing of the error detection operation comprises detecting whether a same pattern repeats in the write data.
However, LEE1 in an analogous art teaches wherein the performing of the error detection operation comprises detecting whether a same pattern repeats in the write data (a column data checking circuitry configured to determine whether all pieces of data outputted from memory cells corresponding to a bit line are identical (same pattern) to each other; and an error correction circuitry configured to determine whether all pieces of data include an error based at least on a type of data, a state of data and an output of the column data checking circuitry, and to resolve the error; LEE1 p. 0028)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of LEE1 by configuring the second error detection operation to determine whether all pieces of column data have a same value.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ pieces of consecutive column data having a same value in the system of Yang in view of Kasai in further view of Ojalvo because LEE2 teaches a column data checking circuitry configured to determine whether all pieces of data outputted from memory cells to determine whether all pieces of data include an error based at least on a type of data, a state of data and an output of the column data checking circuitry, and to resolve the error (LEE1 p. 0028).
Claims 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of SHIRAKAWA (US 20220108754 A1).
As per claim 3, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the operating method of claim 1.
Yang in view of Kasai in further view of Ojalvo does not teach wherein the program command comprises an address indicating an area of the memory cells in the nonvolatile memory device storing 1-bit data.
However, SHIRAKAWA in an analogous art teaches wherein the program command comprises an address indicating an area of the memory cells in the nonvolatile memory device storing 1-bit data (The semiconductor memory includes: a plurality of first blocks each including a memory cell capable of storing data of one bit; a second block including a memory cell capable of storing data of two or more bits; and a sense amplifier including a first latch circuit and a second latch circuit. In a write operation, the controller outputs a set of first data of one page and a first write command, a set of second data of one page and a second write command, and a third write command; SHIRAKAWA p. 0024) (The address register 150 stores an address ADD received from the controller 200. The command register 160 stores a command CMD received from the controller 200. The sequencer 170 controls the entire operation of the NAND flash memory 100, based on the various kinds of information held in the registers; SHIRAKAWA p. 0041-0042)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of SHIRAKAWA by configuring the program command with an address indicating an area of the memory cells in the nonvolatile memory device storing 1-bit data.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ storing 1-bit data in the system of Yang in view of Kasai in further view of Ojalvo because SHIRAKAWA teaches a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits to increase the reliability in data writing is improved (SHIRAKAWA p. 0174).
As per claim 14, Yang in view of Kasai in further view of Ojalvo in further view of SHIRAKAWA, as combined, teaches the operating method of claim 13, wherein the receiving of the program command and the write data from the storage controller comprises receiving a program command comprising an address indicating an area of the memory cells in the nonvolatile memory device storing 1-bit data (The semiconductor memory includes: a plurality of first blocks each including a memory cell capable of storing data of one bit; a second block including a memory cell capable of storing data of two or more bits; and a sense amplifier including a first latch circuit and a second latch circuit. In a write operation, the controller outputs a set of first data of one page and a first write command, a set of second data of one page and a second write command, and a third write command; SHIRAKAWA p. 0024) (The address register 150 stores an address ADD received from the controller 200. The command register 160 stores a command CMD received from the controller 200. The sequencer 170 controls the entire operation of the NAND flash memory 100, based on the various kinds of information held in the registers; p. 0041-0042).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of HUANG et al. (US 20220058070 A1), hereinafter referred as HUANG in further view of Lee et al. (US 20230018681 A1), hereinafter referred as Lee2.
As per claim 4, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the operating method of claim 1, further comprising: performing, by the storage controller, one of: an error correction operation on the error data based on the error data (During the writing process, the encoded data is first written to the page buffer 121. After the memory controller 110 sends a program command to the control circuit 123 in the NV memory 120, the encoded data will be programmed on one or more pages (or super pages) of an NV memory element 122_k of the NV memory (equates an error correction operation); Yang p. 0025).
Yang in view of Kasai in further view of Ojalvo, as combined, does not teach an input/output adjustment operation based on the error data being an uncorrectable error.
However, HUANG in an analogous art teaches an input/output adjustment operation based on the error data being an uncorrectable error (An error event can be detected when the error correcting code fails to correct error in data, i.e. when UECC occurs. The UECC can be related to tight timing margin of memory dies. If the no uncorrectable error event is detected at operation 330, then at operation 380, the processor determines that the initial frequency should be maintained for the controller and the memory die. On the other hand, responsive to detecting an uncorrectable error event at operation 330, the processor proceeds to operation 340, and sets an error threshold criterion for repeating the read operation one or more times. The number of repetition can be set by a counter. At operation 350, the processor adjusts operating frequency of at least one of the memory controller or the memory die to a frequency that is different from the initial frequency. For example, the processor can slow down the controller frequency while keeping the die frequency (adjusting controller/die equates input/output) at the initial level, or, increase the die frequency while keeping the controller frequency at the initial level; HUANG p. 0043-0046).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of HUANG by configuring an input/output adjustment operation based on the error data being an uncorrectable error
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ an input/output adjustment in the system of Yang in view of Kasai in further view of Ojalvo because HUANG teaches a command to read specific data stored at a memory die resulting in UECC during high-speed operations and adaptively correcting that frequency mismatch (HUANG p. 0013).
Yang in view of Kasai in further view of Ojalvo in further view of HUANG, as combined, does not teach transmitting, by the storage controller, a resume command to program the write data based on the error being corrected.
However, Lee2 in an analogous art teaches transmitting, by the storage controller, a resume command to program the write data based on the error being corrected (Aspects of the present disclosure address the above and other deficiencies by sending an auto resume command to the memory component (e.g., storage device) such that the other memory operation does not resume until an auto resume command is received and the read command is executed. A resume continuation command can also be sent after the read command has been executed, when page buffer resources are to be used. The resume continuation can resume the memory operation responsive to whether a checkpoint for resuming the memory operation has been met; Lee2 p. 0014).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo in further view of HUANG with the teachings of Lee2 by configuring transmitting a resume command to program the write data based on the error being corrected. This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ transmitting a resume command in the system of Yang in view of Kasai in further view of Ojalvo in further view of HUANG because Lee2 teaches a processing device, operatively coupled with the memory component, can then send an auto resume command to support the resumption of the other memory operation concurrently with the read data transfer (Lee2 p. 0013).
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2 in further view of Cho et al. (US 9564233 B1), hereinafter referred as Cho.
As per claim 5, Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2, as combined, teaches the operating method of claim 4.
Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2, as combined, does not teach wherein the performing of the input/output adjustment operation comprises adjusting a power supply voltage or an input/output voltage input to the nonvolatile memory device.
However, Cho in an analogous art teaches wherein the performing of the input/output adjustment operation comprises adjusting a power supply voltage or an input/output voltage input to the nonvolatile memory device (A voltage adjustment module adjusts a voltage level applied to one or more source lines connected to the one or more storage cells during a write operation in response to determining a characteristic satisfies a threshold; Cho p. ABST; Col. 1 lines 35-43)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2 with the teachings of Cho by configuring the input/output adjustment operation to adjusting a power supply voltage or an input/output voltage input to the nonvolatile memory device.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ adjusting a power supply voltage or an input/output voltage input in the system of Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2 because Cho teaches adjusting a voltage level for a write operation on a partially programmed block of a nonvolatile storage device to improve the performance and endurance of a partially programmed block 200 of a nonvolatile storage device (Cho Col. 12 lines 65-68).
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2 in further view of Cai et al (US 20180166142 A1), hereinafter referred as Cai, in further view of Kern et al. (US 20090187700 A1), hereinafter referred as Kern.
As per claim 6, Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2, as combined, teaches the operating method of claim 4. Yang in view of Kasai in further view of Ojalvo in further view of HUANG, as combined, does not teach determining, by the storage controller, whether a program count, which is a number of times a program command is transmitted for a same address, is equal to or greater than a threshold value after performing the input/output adjustment operation;
based on a determination that the program count is equal to or greater than the threshold value, determining, by the storage controller, a program failure and storing information about the program failure;
and based on a determination that the program count is less than the threshold value, retransmitting, by the storage controller, the program command and the write data to the nonvolatile memory device.
However, Cai in an analogous art teaches determining, by the storage controller, whether a program count, which is a number of times a program command is transmitted for a same address, is equal to or greater than a threshold value after performing the input/output adjustment operation (ISPP may repeat iterations of the program stage and/or the verify stage. Iterations may be repeated until a maximum number (threshold) of such iterations (e.g., a loop count) has been reached, and/or until the ISPP terminates because all of the cells are correctly programed; Cai p. 0031);
based on a determination that the program count is equal to or greater than the threshold value, determining, by the storage controller, a program failure (The decision state 216 may determine if a maximum number of iterations has been reached. If so, the method 200 moves to the state 218. If not, the method 200 moves back to the state 204. The state 218 reports a program failure; Cai p. 0036) and storing information about the program failure (reports an error count…reports a failure of the programming; Cai p. 0045-0046)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2 with the teachings of Cai by configuring the storage controller to determine whether a program count is equal to, greater than or less than a threshold value after performing the input/output adjustment operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ determining whether a program count has reached, exceeded or fallen short of a threshold value in the system of Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2 because Cai teaches a flash command that reports a count of cell program failures that may (i) implement a polling status command to verify cell programming, (ii) report a total number of cells that failed programming, (iii) provide error reporting on a per chunk basis, (iv) leverage information traditionally available in flash memory, (v) determine the number of errors without triggering a read operation, (vi) reprogram data to known reliable locations if the number of errors is above a threshold, (vii) tolerate errors if the number of errors is below a threshold, (viii) report a total number of cells that failed programming as a chunk of cells, and/or (ix) be implemented as one or more integrated circuits (Cai p. 0015) Kern in the analogous art teaches based on a determination that the program count is less than the threshold value, retransmitting, by the storage controller, the program command and the write data to the nonvolatile memory device (notification of the write operation failure will trigger the system to issue a retarget address, i.e., a new physical address/location to the buffer of the non-volatile device and the device will attempt to write the data to the location within the non-volatile device associated with the retarget address; Kern p. 0010) (Kern also calls it’s a retry logic on the write operation).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2 in further view of Cai with the teachings of Kern by configuring the storage controller to determine whether a program count is equal to, greater than or less than a threshold value after performing the input/output adjustment operation and retransmit the program command.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ determining whether a program count has reached, exceeded or fallen short of a threshold value and retransmitting the program command in the system of Yang in view of Kasai in further view of Ojalvo in further view of HUANG in further view of Lee2 in further view of Cai because Kern teaches write operation retry eliminate the need for the external system buffer, overall cost of the system is minimized, space minimization in terms of board design can be addressed and latencies attributed to transferring the data from the external system buffer to the non-volatile device buffer can be eliminated (Kern p. 0007).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of Himeno (US 4726028 A).
As per claim 7, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the operating method of claim 1. They do not teach wherein the performing of the error detection operation comprises:
performing a first error detection operation based on a first policy to determine whether an error has occurred in the write data;
and based on an error not being detected in the write data based on the first policy, performing a second error detection operation based on a second policy to determine whether an error has occurred in the write data, the second policy being different from the first policy.
However, Himeno in an analogous art teaches wherein the performing of the error detection operation comprises:
performing a first error detection operation based on a first policy to determine whether an error has occurred in the write data (executing an error check in each data block by use of the first error check code and setting an error pointer to all the words in the data block when an error is detected (check code equates policy); Himeno Claim 1);
and based on an error not being detected in the write data based on the first policy, performing a second error detection operation based on a second policy to determine whether an error has occurred in the write data, the second policy being different from the first policy (executing an error check in each data block in which no error is detected by the first error check code, using the second error check code and the third error check code; Himeno Claim 1) (the first error check code is a CRC code. the second and third error check codes are both Reed-Solomon codes (equates first being different than second; Claims 2-3).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of Himeno by configuring the error correction operation ot be based on a first policy and performing a second detection based on an error not being detected in the first.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a second error detection based on thew first not detecting an error in the system of Yang in view of Kasai in further view of Ojalvo because Himeno teaches detecting and correcting error words in a data block with check code (check policies) having a repetition times of the error correction increasing, so that the correcting capability can be improved (Himeno Col. 8 lines 30-34).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of Himeno in further view of Shadmi et al. (US 20200133570 A1), hereinafter referred as Shadmi.
As per claim 8, Yang in view of Kasai in further view of Ojalvo in further view of Himeno, as combined, teaches the operating method of claim 7. They do not teach wherein the first error detection operation comprises:
counting a first value in the write data as a first count and counting a second value in the write data as a second count;
determining whether a difference between the first count and the second count is greater than a threshold value;
determining that the error has occurred in the write data based on the difference between the first count and the second count being greater than the threshold value;
and determining that the error has not occurred based on the difference between the first count and the second count being equal to or less than the threshold value.
However, Shadmi in the analogous art teaches wherein the first error detection operation comprises:
counting a first value in the write data as a first count and counting a second value in the write data as a second count (monitoring a read statistic may include obtaining a count of ones, a count of zeros or the like; Shadmi p. 0092);
determining whether a difference between the first count and the second count is greater than a threshold value (a statistics circuit 502 may include a register, accumulator, or the like, used to store or count the number of ones (or the number of zeros) in the data as the data is read…The threshold circuit 504, in one embodiment, is configured to determine whether the one or more read statistics monitored by the statistics circuit 502 satisfy a threshold for the read operation. For example, in one embodiment, the threshold circuit 504 may compare the one or more read statistics to one or more expected statistics for the data.; Shadmi p. 0091, 0092);
determining that the error has occurred in the write data based on the difference between the first count and the second count being greater than the threshold value (the DMC count represents an even distribution (i.e., 50/50 split) between 0's and l's (or any of the states in the cell) in the data. To the extent that the DMC count deviates too far from the expected value, certain ECC or even uncorrectable ECC (UECC) functions are perform as described herein; Shadmi p. 0125) (whether the DMC count is above the first and second thresholds. In response to a determination that the DMC count is above the first and second thresholds, the method 1000 includes predicting that there is a failure of the decode process, i.e. UECC, and thus foregoing or bypassing the ECC completely; Shadmi p. 0137);
and determining that the error has not occurred based on the difference between the first count and the second count being equal to or less than the threshold value (dynamic read component 150 may proceed normally with a read operation if the read statistic(s) are normal, within an expected or acceptable range, or the like, and may modify, adjust or update a read operation if one or more of the read statistics are outside of acceptable ranges…A read statistic is said to satisfy the threshold if the read statistic is acceptable in comparison to the threshold (e.g., is below a maximum, above a minimum, within a range, or the like), and fails to satisfy the threshold otherwise; Shadmi p. 0094, 0135).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of Shadmi by configuring the first error detection operation with counting two values and comparing them based on a threshold value.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ comparing two values based on a threshold value in the system of Yang in view of Kasai in further view of Ojalvo because Shadmi teaches dynamic read operations where a controller determines whether one or more read statistics satisfy a threshold for a read operation to dynamically modify a read operation based on determining that one or more read statistics fail to satisfy a threshold (Shadmi p. 0006).
As per claim 9, Yang in view of Kasai in further view of Ojalvo in further view of Himeno, as combined, teaches the operating method of claim 7. Shadmi also teaches wherein the first error detection operation comprises:
aligning the write data based on a physical column address (the method 1100 includes performing (1102) de-interleaving of the data from the NAND memory 123. De-interleaving may be performed to uncover the physical order ("physical column address") of the interleaved data; Shadmi p. 0139);
dividing the aligned write data into a plurality of groups (the method 1100 includes portioning the NAND memory 123 into data portions (e.g., chunks) and calculating (1104) a DMC count for each data portion; Shadmi p. 0140);
and counting a first value in each of the plurality of groups as a first count and counting a second value in each of the plurality of groups as a second count (the method 1100 includes portioning the NAND memory 123 into data portions (e.g., chunks) (chunks equates counts) and calculating ("per-group") (1104) a DMC count for each data portion (Shadmi p. 0140). monitoring a read statistic may include obtaining a count of ones (first value), a count of zeros (second value) or the like…calculating a difference between counts of ones and zeroes, a ratio between counts of ones and zeros or the like (Shadmi p. 0092)(count of ones in a chunk equate first count, count of zeros equates second count), and determining, for the plurality of groups, whether a difference between the first count and the second count for each of the plurality of groups is greater than a threshold value determining (1106) whether the DMC count deviates significantly from a 50% of the total bit count in a data portion (Shadmi p. 0141). approximately 50% of the total bit count, when the DMC count is slightly deviated from 50% of the total count and when the DMC count is substantially deviated from 50% of the total count…a significant deviation is a value outside of the range of 40-60% of the total bit count (Shadmi p. 0129) (for each physical chunk, the count-based bit distribution is compared against a permitted threshold or range to determine whether that chink has an excessive imbalance);
determining that the error has occurred based on the difference between the first count and the second count in one or more of the plurality of groups being greater than the threshold value In response to a determination that the DMC count deviates significantly form a 50% of the total bit count, the method 1100 include identifying the data portion as a possible physical defect and forwarding the information to the firmware exception handling module 918 for aiding in further ECC processing of the remainder of the data portions for the NAND memory (Shadmi p. 0141). In response to a determination that the DMC count is above the first and second thresholds, the method 1000 includes predicting that there is a failure of the decode process, i.e. UECC, and thus foregoing or bypassing the ECC completely (Shadmi p. 0137) (an excessive imbalance ("greater than threshold") in at least one data portion causes that portion to be identified as defective and may cause prediction of an ECC/UECC failure);
and determining that the error has not occurred based on the difference between the first count and the second count for each of the plurality of groups being equal to or less than the threshold value (dynamic read component 150 may proceed normally with a read operation if the read statistic(s) are normal, within an expected or acceptable range, or the like, and may modify, adjust or update a read operation if one or more of the read statistics are outside of acceptable ranges (Shadmi p. 0094) (defines satisfying the threshold as being below a maximum or within the acceptable range) Perform data decoding if the DMC count is approximately 50% of the total count (Shadmi p. 0128) (where all chunks remain within the acceptable count-difference range, non is identified ("not occurred") as defective and normal decoding proceeds).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of Himeno in further view of LEE (US 20200226039 A1), hereinafter referred as LEE1.
As per claim 10, Yang in view of Kasai in further view of Ojalvo in further view of Himeno, as combined, teaches the operating method of claim 7. They fail to teach wherein the second error detection operation comprises determining whether all pieces of consecutive column data in the write data have a same value.
However, LEE1 in the analogous art teaches wherein the second error detection operation comprises determining whether all pieces of consecutive column data (plural memory cells which are individually addressable through a row address corresponding to a word line and a column address corresponding to a bit line(consecutive column data)…plural pieces of data outputted from memory cells corresponding to each column address in the target area are the same as each other; LEE1 p. 0041) in the write data have a same value (determine whether all pieces of data outputted from memory cells corresponding to a bit line are identical ("same value") to each other; LEE1 p. 0028, 0042).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of LEE1 by configuring the second error detection operation to determine whether all pieces of column data have a same value.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ pieces of consecutive column data having a same value in the system of Yang in view of Kasai in further view of Ojalvo because LEE2 teaches a column data checking circuitry configured to determine whether all pieces of data outputted from memory cells to determine whether all pieces of data include an error based at least on a type of data, a state of data and an output of the column data checking circuitry, and to resolve the error (LEE p. 0028).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of Himeno in further view of Shadmi in further view of LEE2.
As per claim 11, Yang in view of Kasai in further view of Ojalvo in further view of Himeno, as combined, teaches the operating method of claim 7. Shadmi and LEE2 teaches wherein the second error detection operation comprises:
aligning the write data based on a physical column address (De-interleaving may be performed to uncover the physical order (de-interleaving for physical order equates aligning) of the interleaved data; Shadmi p. 0139);
and determining whether all pieces of consecutive column data in the aligned write data have a same value (The volatile memory may include plural memory cells which are individually addressable through a row address corresponding to a word line and a column address corresponding to a bit line; LEE p. 0041) (determining whether plural pieces of data outputted from memory cells corresponding to each column address in the target area are the same as each other; LEE p. 0043).
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of Lu et al (US 20230266895 A1), hereinafter referred as Lu.
As per claim 12, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the operating method of claim 1. They fail to teach transmitting, by the storage controller, error detection deactivation information to the nonvolatile memory device after the program command is completed.
However, Lu in an analogous art teaches transmitting, by the storage controller, error detection deactivation information to the nonvolatile memory device after the program command is completed (through the specific communication interface, and it is used for sending commands and data between the flash memory device and a processor. The processor is coupled to the I/O circuit, and it is used for controlling the I/O circuit sending a data toggle set-feature signal to the flash memory device to enable, disable (deactivation), or configure a data toggle operation of the flash memory device…in response to a specific read command or a data toggle command transmitted by the flash memory controller; Lu p. 0008).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of Lu by configuring transmitting error detection deactivation information to the nonvolatile memory device after the program command is completed.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ error detection deactivation in the system of Yang in view of Kasai in further view of Ojalvo because Lu teaches sending a data toggle set-feature signal to the flash memory device to enable, disable, or configure a data toggle operation to perform an access operation upon the multiple data units at the first plane and the second plane (Lu p. 0011).
Claims 15, 16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of Shadmi.
As per claim 15, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the operating method of claim 13. Shadmi teaches wherein the performing of the error detection operation comprises:
counting a first value in the write data as a first count and counting a second value in the write data as a second count the method 1100 includes portioning the NAND memory 123 into data portions (e.g., chunks) (chunks equates counts) and calculating ("per-group") (1104) a DMC count for each data portion (Shadmi p. 0140). monitoring a read statistic may include obtaining a count of ones (first value), a count of zeros (second value) or the like…calculating a difference between counts of ones and zeroes, a ratio between counts of ones and zeros or the like (Shadmi p. 0092)(count of ones in a chunk equate first count, count of zeros equates second count);
determining whether a difference between the first count and the second count is greater than a threshold value determining (1106) whether the DMC count deviates significantly from a 50% of the total bit count in a data portion (Shadmi p. 0141). approximately 50% of the total bit count, when the DMC count is slightly deviated from 50% of the total count and when the DMC count is substantially deviated from 50% of the total count…a significant deviation is a value outside of the range of 40-60% of the total bit count (Shadmi p. 0129) (for each physical chunk, the count-based bit distribution is compared against a permitted threshold or range to determine whether that chink has an excessive imbalance);
determining that the error has occurred in the write data based on the difference between the first count and the second count being greater than the threshold value In response to a determination that the DMC count deviates significantly form a 50% of the total bit count, the method 1100 include identifying the data portion as a possible physical defect and forwarding the information to the firmware exception handling module 918 for aiding in further ECC processing of the remainder of the data portions for the NAND memory (Shadmi p. 0141). In response to a determination that the DMC count is above the first and second thresholds, the method 1000 includes predicting that there is a failure of the decode process, i.e. UECC, and thus foregoing or bypassing the ECC completely (Shadmi p. 0137) (an excessive imbalance ("greater than threshold") in at least one data portion causes that portion to be identified as defective and may cause prediction of an ECC/UECC failure);
and determining that the error has not occurred in the write data based on the difference between the first count and the second count being equal to or less than the threshold value (dynamic read component 150 may proceed normally with a read operation if the read statistic(s) are normal, within an expected or acceptable range, or the like, and may modify, adjust or update a read operation if one or more of the read statistics are outside of acceptable ranges (Shadmi p. 0094) (defines satisfying the threshold as being below a maximum or within the acceptable range) Perform data decoding if the DMC count is approximately 50% of the total count (Shadmi p. 0128) (where all chunks remain within the acceptable count-difference range, non is identified ("not occurred") as defective and normal decoding proceeds).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of Shadmi by configuring the first error detection operation with counting two values and comparing them based on a threshold value.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ comparing two values based on a threshold value in the system of Yang in view of Kasai in further view of Ojalvo because Shadmi teaches dynamic read operations where a controller determines whether one or more read statistics satisfy a threshold for a read operation to dynamically modify a read operation based on determining that one or more read statistics fail to satisfy a threshold (Shadmi p. 0006).
As per claim 16, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the operating method of claim 13. Shadmi teaches wherein the performing of the error detection operation comprises:
aligning the write data based on a physical column address (the method 1100 includes performing (1102) de-interleaving of the data from the NAND memory 123. De-interleaving may be performed to uncover the physical order ("physical column address") of the interleaved data; Shadmi p. 0139);
dividing the aligned write data into a plurality of groups (the method 1100 includes portioning the NAND memory 123 into data portions (e.g., chunks) and calculating (1104) a DMC count for each data portion; Shadmi p. 0140);
counting a first value in each of the plurality of groups as a first count and counting a second value in each of the plurality of groups as a second count (the method 1100 includes portioning the NAND memory 123 into data portions (e.g., chunks) (chunks equates counts) and calculating ("per-group") (1104) a DMC count for each data portion (Shadmi p. 0140). monitoring a read statistic may include obtaining a count of ones (first value), a count of zeros (second value) or the like…calculating a difference between counts of ones and zeroes, a ratio between counts of ones and zeros or the like (Shadmi p. 0092) (count of ones in a chunk equate first count, count of zeros equates second count);
determining, for the plurality of groups, whether a difference between the first count and the second count for each of the plurality of groups is greater than a threshold value determining (1106) whether the DMC count deviates significantly from a 50% of the total bit count in a data portion (Shadmi p. 0141). approximately 50% of the total bit count, when the DMC count is slightly deviated from 50% of the total count and when the DMC count is substantially deviated from 50% of the total count…a significant deviation is a value outside of the range of 40-60% of the total bit count (Shadmi p. 0129) (for each physical chunk, the count-based bit distribution is compared against a permitted threshold or range to determine whether that chink has an excessive imbalance);
determining that the error has occurred based on the difference between the first count and the second count in one or more of the plurality of groups being greater than the threshold value In response to a determination that the DMC count deviates significantly form a 50% of the total bit count, the method 1100 include identifying the data portion as a possible physical defect and forwarding the information to the firmware exception handling module 918 for aiding in further ECC processing of the remainder of the data portions for the NAND memory (Shadmi p. 0141). In response to a determination that the DMC count is above the first and second thresholds, the method 1000 includes predicting that there is a failure of the decode process, i.e. UECC, and thus foregoing or bypassing the ECC completely (Shadmi p. 0137) (an excessive imbalance ("greater than threshold") in at least one data portion causes that portion to be identified as defective and may cause prediction of an ECC/UECC failure);
and determining that the error has not occurred based on the difference between the first count and the second count for each of the plurality of groups being equal to or less than the threshold value (dynamic read component 150 may proceed normally with a read operation if the read statistic(s) are normal, within an expected or acceptable range, or the like, and may modify, adjust or update a read operation if one or more of the read statistics are outside of acceptable ranges (Shadmi p. 0094) (defines satisfying the threshold as being below a maximum or within the acceptable range) Perform data decoding if the DMC count is approximately 50% of the total count (Shadmi p. 0128) (where all chunks remain within the acceptable count-difference range, non is identified ("not occurred") as defective and normal decoding proceeds).
As per claim 19, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the nonvolatile memory device of claim 18. Shadmi teaches wherein the error detection circuit is further configured to:
count a first value in the write data as a first count and count a second value in the write data as a second count (the method 1100 includes portioning the NAND memory 123 into data portions (e.g., chunks) (chunks equates counts) and calculating ("per-group") (1104) a DMC count for each data portion (Shadmi p. 0140). monitoring a read statistic may include obtaining a count of ones (first value), a count of zeros (second value) or the like…calculating a difference between counts of ones and zeroes, a ratio between counts of ones and zeros or the like (Shadmi p. 0092)(count of ones in a chunk equate first count, count of zeros equates second count), determine whether a difference between the first count and the second count is greater than a threshold value (determining (1106) whether the DMC count deviates significantly from a 50% of the total bit count in a data portion (Shadmi p. 0141). approximately 50% of the total bit count, when the DMC count is slightly deviated from 50% of the total count and when the DMC count is substantially deviated from 50% of the total count…a significant deviation is a value outside of the range of 40-60% of the total bit count (Shadmi p. 0129) (for each physical chunk, the count-based bit distribution is compared against a permitted threshold or range to determine whether that chink has an excessive imbalance), determine that the error has occurred based on the difference between the first count and the second count being greater than the threshold value (In response to a determination that the DMC count deviates significantly form a 50% of the total bit count, the method 1100 include identifying the data portion as a possible physical defect and forwarding the information to the firmware exception handling module 918 for aiding in further ECC processing of the remainder of the data portions for the NAND memory (Shadmi p. 0141). In response to a determination that the DMC count is above the first and second thresholds, the method 1000 includes predicting that there is a failure of the decode process, i.e. UECC, and thus foregoing or bypassing the ECC completely (Shadmi p. 0137) (an excessive imbalance ("greater than threshold") in at least one data portion causes that portion to be identified as defective and may cause prediction of an ECC/UECC failure), and determine that the error has not occurred based on the difference between the first count and the second count being equal to or less than the threshold value (dynamic read component 150 may proceed normally with a read operation if the read statistic(s) are normal, within an expected or acceptable range, or the like, and may modify, adjust or update a read operation if one or more of the read statistics are outside of acceptable ranges (Shadmi p. 0094) (defines satisfying the threshold as being below a maximum or within the acceptable range) Perform data decoding if the DMC count is approximately 50% of the total count (Shadmi p. 0128) (where all chunks remain within the acceptable count-difference range, non is identified ("not occurred") as defective and normal decoding proceeds).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Yang in view of Kasai in further view of Ojalvo with the teachings of Shadmi by configuring the first error detection operation with counting two values and comparing them based on a threshold value.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ comparing two values based on a threshold value in the system of Yang in view of Kasai in further view of Ojalvo because Shadmi teaches dynamic read operations where a controller determines whether one or more read statistics satisfy a threshold for a read operation to dynamically modify a read operation based on determining that one or more read statistics fail to satisfy a threshold (Shadmi p. 0006).
As per claim 20, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the nonvolatile memory device of claim 18. Shadmi teaches wherein the error detection circuit is further configured:
align the write data based on a physical column address (the method 1100 includes performing (1102) de-interleaving of the data from the NAND memory 123. De-interleaving may be performed to uncover the physical order ("physical column address") of the interleaved data; Shadmi p. 0139), divide the aligned write data into a plurality of groups (the method 1100 includes portioning the NAND memory 123 into data portions (e.g., chunks) and calculating (1104) a DMC count for each data portion; Shadmi p. 0140), count a first value in each of the plurality of groups as a first count and count a second value in each of the plurality of groups as a second count (the method 1100 includes portioning the NAND memory 123 into data portions (e.g., chunks) (chunks equates counts) and calculating ("per-group") (1104) a DMC count for each data portion (Shadmi p. 0140). monitoring a read statistic may include obtaining a count of ones (first value), a count of zeros (second value) or the like…calculating a difference between counts of ones and zeroes, a ratio between counts of ones and zeros or the like (Shadmi p. 0092)(count of ones in a chunk equate first count, count of zeros equates second count), determine, for the plurality of groups, whether a difference between the first count and the second count is greater than a threshold value (determining (1106) whether the DMC count deviates significantly from a 50% of the total bit count in a data portion (Shadmi p. 0141). approximately 50% of the total bit count, when the DMC count is slightly deviated from 50% of the total count and when the DMC count is substantially deviated from 50% of the total count…a significant deviation is a value outside of the range of 40-60% of the total bit count (Shadmi p. 0129) (for each physical chunk, the count-based bit distribution is compared against a permitted threshold or range to determine whether that chink has an excessive imbalance), determine that the error has occurred based on the difference between the first count and the second count in one or more of the plurality of groups being greater than the threshold value (In response to a determination that the DMC count deviates significantly form a 50% of the total bit count, the method 1100 include identifying the data portion as a possible physical defect and forwarding the information to the firmware exception handling module 918 for aiding in further ECC processing of the remainder of the data portions for the NAND memory (Shadmi p. 0141). In response to a determination that the DMC count is above the first and second thresholds, the method 1000 includes predicting that there is a failure of the decode process, i.e. UECC, and thus foregoing or bypassing the ECC completely (Shadmi p. 0137) (an excessive imbalance ("greater than threshold") in at least one data portion causes that portion to be identified as defective and may cause prediction of an ECC/UECC failure), and determine that the error has not occurred based on the difference between the first count and the second count for each of the plurality of groups being equal to or less than the threshold value (dynamic read component 150 may proceed normally with a read operation if the read statistic(s) are normal, within an expected or acceptable range, or the like, and may modify, adjust or update a read operation if one or more of the read statistics are outside of acceptable ranges (Shadmi p. 0094) (defines satisfying the threshold as being below a maximum or within the acceptable range) Perform data decoding if the DMC count is approximately 50% of the total count (Shadmi p. 0128) (where all chunks remain within the acceptable count-difference range, non is identified ("not occurred") as defective and normal decoding proceeds).
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Kasai in further view of Ojalvo in further view of LEE2.
As per claim 17, Yang in view of Kasai in further view of Ojalvo, as combined, teaches the operating method of claim 13. LEE2 teaches wherein the performing of the error detection operation comprises determining whether all pieces of consecutive column data (plural memory cells which are individually addressable through a row address corresponding to a word line and a column address corresponding to a bit line(consecutive column data)…plural pieces of data outputted from memory cells corresponding to each column address in the target area are the same as each other; LEE p. 0041) in the write data have a same value (determine whether all pieces of data outputted from memory cells corresponding to a bit line are identical ("same value") to each other; LEE p. 0028, 0042).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts of record teach:
KANNO et al. (US 20230139971 A1) teaches a4:47 PM semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
VITTAL PRABHU et al. (US 20200250028 A1) teaches a memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.
KIM (US 20060050576 A1) teaches a NAND flash memory device according to some embodiments includes a cell array, a page buffer configured to copyback read the data in the cell array, and an error detector for detecting errors that occur during the copyback reading and for generating a detection signal. Detecting errors is performed concurrently with a copyback program operation and completes before finishing a copyback program verify operation. The data stored in the page buffer may be copyback programmed when the detection signal is a pass signal. The copyback operation may end without executing the copyback program operation when the detection signal is a fail signal.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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