DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of the amendment to claims 1 and 12, a new reference of Kim et al. (US Pub. 2025/0285584 A1) is applied to a new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5-8, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Pub. 2023/0032883 A1) in view of Kim et al. (US Pub. 2025/0285584 A1).
Regarding claim 1; Park teaches a display device (a display device 1000, Fig.1), comprising:
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(Fig.5 of Park reproduced)
a timing controlling unit (a controller 500) configured to generate an image data,
a data control signal and a gate control signal (para. [0058-0062], the controller 500 is configured to generate image data RGB, a first control signal SCS, a second control signal ECS, and a third control signal DCS);
a data driving unit (a data driver 400) configured to generate a data signal using the image data and the data control signal (para. [0069]);
a gate driving unit (a scan driver 200 and an emission driver 300) configured to generate a plurality of scan signals and an emission signal using the gate control signal (para. [0063 and 0066], the scan driver 200 and the emission driver 300 are configured to generate a plurality of scan signals S11 to S4n and a plurality of emission control signal E1 to En); and
a display panel (a display panel 100) configured to display an image using the data signal, the plurality of scan signals and the emission signal (para. [0057]),
wherein the emission signal (para. [0011, 0060, and 0061], Fig.5 shows an emission signal Ei corresponding to different dimming value DBV indicating a maximum display luminance) includes a plurality of cycles each having a duty-on period (e.g., an emission period EP1 of a first cycle as shown in Fig.5 reproduced above) and an duty-off period (e.g., a non-emission period NEP1 of the first cycle, Fig.5) during one frame (Fig.5), and wherein duty ratios of at least two of the plurality of cycles are different from each other (Fig.5, a duty ratio of at least two cycles are different from each other. For example, duty ratios of two cycles corresponding to a first dimming value DBV1 are different from those corresponding to a second dimming value DBV2).
Park does not teach a first width of a duty-off period including a reset period is smaller than a second width of a duty-off period not including the reset period.
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(Fig.11 of Kim reproduced)
Kim teaches a first width of a duty-off period including a reset period is smaller than a second width of a duty-off period not including the reset period (Fig.11, para. [0152], a first width PW10 of an off-section of an emission control signal EM in an active period AP is smaller than a second width PW11 of an off-section of the emission control signal EM in a blank period BP1. In Figs. 3 and 18, para. [0108 and 0110], in the active period AP, scan signals Gl1 to Gln are applied to transistor T4 to supply an initialization voltage VINIT to node N2. In the blank period, the scan signals GI1 to Gin are maintained at an inactive level. In other words, in the blank period, the initialization voltage VINT is not supplied to initialize the node N2. Therefore, Kim teaches that the first width (i.e., PW10) includes a reset period (i.e., an initialization period). Kim further teaches that the second width (i.e., PW11) does not include a reset period (i.e., initialization period)).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Park to include the teaching of Kim of providing a second pulse width of an emission control signal in a blank period having a greater value than that in an active period. The motivation would have been in order to improve image quality by operating the display device at various driving frequencies (Kim, para. [0005-0007]).
Regarding claim 2; Park in view of Kim teaches the display device of claim 1 as discussed above. Park further teaches a duty ratio of one of the plurality of cycles having a reset period is greater than a duty ratio of another of the plurality of cycles where the reset period is omitted (Fig.5 reproduced above, the first emission period EP1 of a first cycle corresponding to the first dimming value DBV1 includes a reset period. The first emission period EP1 of the first cycle corresponding to second dimming value DBV2 does not include a reset period. The duty ratio of the first cycle corresponding to the first dimming value DBV1 is greater than that of the first cycle corresponding to second dimming value DBV2).
Regarding claim 5; Park in view of Kim teaches the display device of claim 1 as discussed above. Park further teaches the plurality of scan signals include a scan1 signal (a second scan signal S2i), an odd scan2 signal (an odd-numbered fourth scan signal S4i), an even scan2 signal (an even-numbered fourth scan signal S4i), a scan3 signal (a first scan signal S1i) and a scan4 signal (a third scan signal S3i), wherein the display panel includes a plurality of subpixels (Fig.1), and wherein each of the plurality of subpixels (Fig.3 shows a pixel circuit 10) comprises:
a storage capacitor (a storage capacitor Cst) connected to a high level voltage (a first driving power source VDD);
a first transistor (a first transistor M1) configured to be switched according to a voltage of a first capacitor electrode of the storage capacitor (Fig.3, para. [0086]);
a second transistor (a second transistor M2) configured to be switched according to one of the odd scan2 signal and the even scan2 signal and connected to the data signal and the first transistor (Fig.3, the second transistor M2 is controlled by the fourth scan signal S4i. The fourth scan signals S4i would comprise odd-numbered fourth scan signals S4(2i+1) and even-numbered fourth scan signals S4(2i));
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(Fig.3 of Park reproduced)
a third transistor (a third transistor M3) configured to be switched according to the scan1 signal (Fig.3, the third transistor M3 is controlled by the second scan signal S2i) and connected to the storage capacitor and the first transistor (see Fig.3);
a fourth transistor (a seventh transistor M7) configured to be switched according to the scan4 signal (Fig.3, the seventh transistor M7 is controlled by the third scan signal S3i) and connected to the storage capacitor (the storage capacitor Cst) and an initial voltage (first initialization voltage Vint1);
a fifth transistor (a fifth transistor M5) configured to be switched according to the emission signal (an emission control signal Ei) and connected to the high level voltage (VDD) and the first transistor (the first transistor M1);
a sixth transistor (a sixth transistor M6) configured to be switched according to the emission signal (the emission control signal Ei) and connected to the first transistor (first transistor M1);
a seventh transistor (an eighth transistor M8) configured to be switched according to the scan3 signal (first scan signal S1i) and connected to an anode reset voltage (second initialization voltage Vint2) and the sixth transistor (the sixth transistor M6);
an eighth transistor (a fourth transistor M4) configured to be switched according to the scan3 signal (first scan signal S1i) and connected to a stress voltage (a bias voltage VEH) and the first transistor (first transistor M1); and
a light emitting diode (a light emitting element LD) connected between the sixth transistor (the sixth transistor M6) and a low level voltage (a second driving power source VSS).
Regarding claim 6; Park in view of Kim teaches the display device of claim 5 as discussed above. Park further teaches at least one of the first to eighth transistors is an oxide semiconductor thin film transistor (para. [0064 and 0104-0105]).
Regarding claim 7; Park in view of Kim teaches the display device of claim 5 as discussed above. Park further teaches the plurality of cycles include first, second, third and fourth cycles, wherein the duty-off period of the first and third cycles includes first, second, third, fourth, fifth and sixth periods,
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Third period)][AltContent: connector][AltContent: textbox (First period)][AltContent: arrow]
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(Fig.4 of Park reproduced)
wherein, during the first period (Fig.4, within a period P1, a first period corresponding to a duration when the first scan signal S1i is low (e.g., PW1, Fig.4)), the first, third, seventh and eighth transistors are turned on (Figs.3 and 4, when the first scan signal S1i is low and the second scan signal S2i is high; the first transistor M1, the third transistor M3, the eight transistor M8, and the fourth transistor M4 are turned on), the second, fourth, fifth and sixth transistors are turned off (Fig.4, during the first period, the third scan signal S3i is low and the fourth scan signal S4i is high. Accordingly; the second transistor M2, the seventh transistor M7, the fifth transistor M5, and the sixth transistor M6 are turned off), the stress voltage (the bias voltage VEH) is applied to first, third and second nodes (Fig.3, first node N1, second node N2, and third node N3), and the anode reset voltage (the second initialization voltage Vinit12) is applied to a fourth node (a fourth node N4),
wherein, during the second period (a second period P2), the fourth transistor is turned on (during the second period P2, the seventh transistor M7 is turned on by third scan signal S3i), the first, second, third, fifth, sixth, seventh and eighth transistors are turned off (during the second period P2; the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor m6, the eight transistor M8, and the fourth transistor M4 are turned off), and the initial voltage (the first initialization voltage Vinit1) is applied to the second node (second node N2),
wherein, during the third period (a third period as illustrated in Fig.4 above. During the third period, the second scan signal S2i and the third scan signal S3i are high), the first, third and fourth transistors are turned on (During the third period; the first transistor M1, the third transistor M3, and the seventh transistor M7 are turned on), the second, fifth, sixth, seventh and eighth transistors are turned off (During the third period; the second transistor M2, the fifth transistor M5, the sixth transistor M6, the eight transistor M8, and the fourth transistor M4 are turned off), and the initial voltage is applied to the second, third and first nodes (Because the seventh transistor M7 is turned on, the first initialization voltage Vint1 is applied to the third node N3, second node N2, and first node N1),
wherein, during the fourth period (a fourth period as illustrated in Fig.4 above. The fourth period is corresponding to a duration when the fourth scan signal S4i is low), the first, second and third transistors are turned on (During the fourth period; the first transistor M1, the second transistor M2, and the third transistor M3 are turned on), the fourth, fifth, sixth, seventh and eighth transistors are turned off (During the fourth period; the seventh transistor M7, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, and the fourth transistor M4 are turned off), and the data signal is applied to the second nodes (the data signal is applied to the second node N2 when the first transistor M1 is turned on),
wherein, during the fifth period, the first, second and third transistors are turned on, the fourth, fifth, sixth, seventh and eighth transistors are turned off, and the data signal is applied to the second node (similar to the fourth period), and
wherein, during the sixth period (a period P4, Fig.4), the first, seventh and eighth transistors are turned on (During the period P4, the first transistor M1, the eight transistor M8, and the fourth transistor M4 are turned on), the second, third, fourth, fifth and sixth transistors are turned off (During the period P4; the second transistor M2, the third transistor M3, the seventh transistor M7, the fifth transistor M5, and the sixth transistor M6 are turned off), the stress voltage (the bias voltage VEH) is applied to the first and third nodes (During the period P4, the bias voltage VEH is applied to the second node N2 because the fourth transistor M4 is turned on), and the anode reset voltage (the second initialization voltage Vint2) is applied to the fourth node (the second initialization voltage Vint2 is applied ty the fourth node N4 because the eight transistor M8 is turned on).
Regarding claim 8; Park in view of Kim teaches the display device of claim 7 as discussed above. Park further teaches the duty-off period of the second and fourth cycles includes seventh, eighth, ninth and tenth periods, wherein, during the seventh period (a seventh period as shown in Fig.4 reproduced below. The seventh period is a duration when the second scan signal S2i is low and the third scan signal S3i is high), the fourth transistor is turned on (During the seventh period, the seventh transistor M7 is turned on), the first, second, third, fifth, sixth, seventh and eighth transistors are turned off (the first transistor M2, the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, and the fourth transistor M4 are turned off), and the initial voltage is applied to the second node (the first initialization voltage Vinit1 is applied to the third node N3),
wherein, during the eighth period (an eighth period after the seventh period as illustrated in Fig.4 below. The eight period is a duration when the second scan signal S2i and the third scan signal S3i are high), the first, third and fourth transistors are turned on (During the eight period; the first transistor M1, the third transistor M3, and the second transistor M7 are turned on), the second, fifth, sixth, seventh and eighth transistors are turned off (During the eighth period; the second transistor M2, the fifth transistor M5, the sixth transistor M6, the eight transistor M8, and the fourth transistor M4 are turned off), and the initial voltage is applied to the second, third and first nodes (the first initialization voltage Vint1 is applied to the third node N2, the second node N2, and the first node N1),
[AltContent: textbox (Nineth period)][AltContent: arrow][AltContent: textbox (Eighth period)][AltContent: textbox (Seventh period)][AltContent: arrow][AltContent: connector][AltContent: arrow][AltContent: arrow]
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wherein, during the ninth period (a nineth period during which the fourth scan signal S4i is low), the first, second and third transistors are turned on (During the nineth period, the first transistor M1, the second transistor M2, and the third transistor m3 are turned on), the fourth, fifth, sixth, seventh and eighth transistors are turned off (During the nineth period; the seventh transistor M7, the fifth transistor M5, the sixth transistor M6, the eight transistor M8, and the fourth transistor M4 are turned off), and the data signal is applied to the second node (the data signal is applied to the third node N3), and
wherein, during the tenth period, the first, second and third transistors are turned on, the fourth, fifth, sixth, seventh and eighth transistors are turned off, and the data signal is applied to the second node (similar to the nineth period).
Regarding claim 12; Park in view of Kim teaches a method of driving a display device including a timing controlling unit (a controller 500, Fig.1), a data driving unit (a data driver 400), a gate driving unit (a scan driver 200 and an emission driver 300) and a display panel (a display panel 100), comprising: during a duty-on period (Fig.4, an emission period EP) of each of a plurality of cycles of one frame, emitting a light by a subpixel of the display panel (Fig.4, a light emitting device LD emits light during an emission period EP); and during a duty-off period of each of the plurality of cycles, applying a data signal to the subpixel of the display panel, wherein duty ratios of at least two of the plurality of cycles are different from each other (similar to the analysis of claim 1, Fig.4, para. [0121-0135], during period P3, a second transistor M2 is turned on when a fourth scan signal S4i is low to connect the data line Dj to a first node N1), and wherein a first width of a duty-off period including a reset period is smaller than a second width of a duty-off period not including the reset period (similar to the analysis of claim 1).
Regarding claim 13; Park in view of Kim teaches the method of claim 12 as discussed above. The limitation of claim 13 is substantially similar to claim 2. Accordingly, claim 13 is rejected based on a similar analysis as the rejection of claim 2.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Pub. 2023/0032883 A1) in view of Kim et al. (US Pub. 2025/0285584 A1) as applied to claim 1 above; further in view of Zhang et al. (US Pub. 2024/0379045 A1).
Regarding claim 9; Park in view of Kim teaches the display device of claim 1 as discussed above. Park further teaches the plurality of scan signals include a scan1 signal, an odd scan2 signal, an even scan2 signal, a scan3 signal and a scan4 signal (see Fig.3 and the analysis of claim 1).
Park does not teach the gate driving unit includes first and second gate driving units disposed at both sides of the display panel, wherein the first gate driving unit includes a scan1 block generating the scan1 signal, an odd scan2 block generating the odd scan2 signal, an even scan2 block generating the even scan2 signal and a scan3 block generating the scan3 signal, and wherein the second gate driving unit includes an odd scan2 block generating the odd scan2 signal, an even scan2 block generating the even scan2 signal, a scan4 block generating the scan4 signal and an emission block generating the emission signal.
Zhang teaches the gate driving unit (Fig.14, a gate driving unit 41) includes first and second gate driving units (Fig.14, the gate driving unit 41 comprises a first driving unit and a second gate driving unit) disposed at both sides of the display panel (Fig.14), wherein the first gate driving unit (the second gate driving unit) includes a scan1 block (a second gate driving block 412) generating the scan1 signal (Figs. 1 and 14, para. [0134], the second gate driving block 412 generates first scan signal 32 to control a fourth transistor T4), an odd scan2 block (an odd four gate driving block, as shown in Fig.14 below) generating the odd scan2 signal (the odd four gate driving block 414 generates third scanning signal 34 to control a second transistor T2), an even scan2 block generating the even scan2 signal (an even fourth gate driving block 414 generates an even second scanning signal 34 to control the second transistor T2) and a scan3 block generating the scan3 signal (a fifth gate driving block 415 generates a fourth scanning signal 34 to control transistors T7 and T8), and wherein the second gate driving unit (first gate driving unit) includes an odd scan2 block generating the odd scan2 signal (similar to the fourth gate driving block of the second gate driving unit), an even scan2 block generating the even scan2 signal (similar to the fourth gate driving block of the second gate driving unit), a scan4 block generating the scan4 signal (a first gate driving block 411 generates a first scanning signal 31 to control a transistor T3) and an emission block generating the emission signal (a third gate driving block 413 generates a light-emitting control signal 33 to control transistors T5 and T6).
[AltContent: arrow][AltContent: textbox (Display panel)][AltContent: rect][AltContent: textbox (Even fourth gate driving blocks)][AltContent: textbox (Odd fourth gate driving blocks)][AltContent: textbox (Second gate driving unit)][AltContent: arrow][AltContent: rect][AltContent: textbox (First gate driving unit)][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]
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(Fig.14 of Zhang reproduced)
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Park to include the teaching of Zhang of arranging gate driving units evenly on both sides of a display panel. The motivation would have been in order to facilitate the manufacturing and obtain a preferred design.
Regarding claim 10; Park in view of Kim and Zhang teaches the display device of claim 9 as discussed above. Park does not teach the scan1 block is disposed farther from the display panel than the scan3 block, or the scan3 block is disposed farther from the display panel than the scan1 block, and wherein the scan4 block is disposed farther from the display panel than the emission block, or the emission block is disposed farther from the display panel than the scan4 block.
Zhang teaches the scan1 block is disposed farther from the display panel than the scan3 block, or the scan3 block is disposed farther from the display panel than the scan1 block (Fig.14, the fifth gate driving block 415 is disposed farther from the display panel than the second gate driving block 412), and wherein the scan4 block is disposed farther from the display panel than the emission block, or the emission block is disposed farther from the display panel than the scan4 block (Fig.14, the third gate driving block 413 is disposed farther from the display panel than the first gate driving block 411).
The motivation is the same as the rejection of claim 9.
Allowable Subject Matter
Claim 11 is allowed.
Claims 3-4, 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art fails to teach all limitations recited in claims 3, 11, 14 and 15.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NGUYEN H TRUONG/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623