Detailed Action
Status of Claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claims 1-20 are rejected.
This Action is Non-Final.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/19/2024, 02/11/2025, 08/01/2025, 09/03/2025, 09/10/2025, 11/13/2025 and 02/04/2026, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over CHRYSOS et al.(US Patent Application Pub. No: 20220100680 A1) in view of BANIN et al.(US Patent Application Pub. No: 20230090431 A1) .
As per claim 1,CHRYSOS teaches an integrated circuit (IC) [Fig.2, a computing system 201], comprising:
a plurality of circuit blocks including a first circuit block and a second circuit block [Paragraphs 0339-0340,… operations include, at a first block, loading dataflow operation entries for a dataflow graph into a dataflow driven accelerator, …., a graph station circuit comprising a plurality of dataflow operation entries that each include a respective ready field that indicates when an input operand for a dataflow operation is available in the register file. In this embodiment, the operations further include, at a second block,…]; and
a plurality of dataflow gaskets electrically connected by a network of gasket interconnect, the plurality of dataflow gaskets comprising a source gasket comprising an output memory coupled to the first circuit block [Pargaraphs 0185, The interconnect network is depicted as circuit switched, statically configured communications channels. For example, a set of channels coupled together by a switch (e.g., switch 610 in a first network and switch 611 in a second network). The first network and second network may be separate or coupled together.], and a destination gasket comprising an input memory coupled to the second circuit block [Paragraph 0215, … multiplexer 3.3C08 is provided with a configuration value from configuration storage (e.g., register) 3.3C06 to cause the multiplexer 3.3C08 to source data from one of more inputs (e.g., with those inputs being coupled to respective PEs or other CSA components).].
CHRYSOS does not explicitly disclose wherein the source gasket is configured to communicate with the destination gasket over the network using a push mode and a pull mode,
wherein a transition from the pull mode to the push mode occurs in response to a data low trigger signal activated by the source gasket and a space high qualifier signal activated by the destination gasket, and
wherein a transition from the push mode to the pull mode occurs in response to a space low trigger signal activated by the destination gasket and a data high qualifier signal activated by the source gasket.
BANIN discloses wherein the source gasket is configured to communicate with the destination gasket over the network using a push mode and a pull mode [Paragraphs 2267-2268, …, if a gasket circuit receives a command from the PCIe controller to change to a specific power state according to the PCIe protocol, the gasket circuit may select a power state (power mode, mode of operation) of the STEP protocol according to a predefined mapping scheme and control the STEP physical layer circuitry to change to the selected power state (power mode, mode of operation) of the STEP protocol.],
wherein a transition from the pull mode to the push mode occurs in response to a data low trigger signal activated by the source gasket and a space high qualifier signal activated by the destination gasket [Paragraphs 0358-0359, The detection circuit 108 is configured generate a trigger signal when no data is identified to be in the first data or the second data. The detection circuit 108 may be coupled to the demodulation circuit 106 or, as illustrated in FIG. 1, to the processing circuit 104.], and
wherein a transition from the push mode to the pull mode occurs in response to a space low trigger signal activated by the destination gasket and a data high qualifier signal activated by the source gasket [Paragraphs 2231;2257, For converting the standard PIPE interface of the PCIe controller 4825 to the proprietary STEP controller interface, the semiconductor die 4800 comprises a gasket circuit 4830 configured to convert between the PIPE interface and the proprietary STEP controller interface (to convert between first and second interface protocols). The gasket circuit 4830 may, e.g., convert data signals and/or control signals/commands of the PIPE interface to data signals and/or control signals/ commands of the STEP controller interface, and vice versa.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include BANIN’s apparatus for generating data signal for Serial Time Encoded Phy (STEP) interconnect into CHRYSOS’s configurable hardware accelerator apparatus for the benefit of enables high throughput with low power requirements by utilizing time encoding to modulate digital pulses and transfer multiple bits for each signal edge present in data signal transmitted via transmission link of interconnect; and the need for separate clock lane or clock recovery circuit is eliminated (BANIN,[0313]) to obtain the invention as specified in claim 1.
As per claim 2, CHRYSOS and BANIN teach all the limitations of claim 1 above, where BANIN teaches, an IC, wherein the data low trigger signal is activated when available data in the output memory of the source gasket is less than a data low threshold [BANIN, Paragraphs 0358-0359, The detection circuit 108 is configured generate a trigger signal when no data is identified to be in the first data or the second data. The detection circuit 108 may be coupled to the demodulation circuit 106 or, as illustrated in FIG. 1, to the processing circuit 104.].
As per claim 3, CHRYSOS and BANIN teach all the limitations of claim 2 above, where BANIN teaches, an IC, wherein the space high qualifier signal is activated when available space in the input memory of the destination gasket is greater than a space high threshold [BANIN, Paragraphs 0358-0359, The detection circuit 108 is configured generate a trigger signal when no data is identified to be in the first data or the second data. The detection circuit 108 may be coupled to the demodulation circuit 106 or, as illustrated in FIG. 1, to the processing circuit 104.].
As per claim 4, CHRYSOS and BANIN teach all the limitations of claim 3 above, where BANIN teaches, an IC, wherein the space low trigger signal is activated when the available space in the input memory of the destination gasket is less than a space low threshold [BANIN, Paragraphs 0358-0359, The detection circuit 108 is configured generate a trigger signal when no data is identified to be in the first data or the second data. The detection circuit 108 may be coupled to the demodulation circuit 106 or, as illustrated in FIG. 1, to the processing circuit 104.].
As per claim 5, CHRYSOS and BANIN teach all the limitations of claim 4 above, where BANIN teaches, an IC, wherein the data high qualifier signal is activated when the available data in the output memory of the source gasket is greater than a data high threshold [BANIN, Paragraph 2481-2484, ….wherein the first time period is longer than a payload data threshold, the second time period is shorter than a payload data threshold, wherein the third time period is longer than the payload data threshold and different from the first time period, and wherein the fourth time period is substantially equal to the second time period;…].
As per claim 6, CHRYSOS and BANIN teach all the limitations of claim 3 above, where BANIN teaches, an IC, wherein the space high threshold is twice the data low threshold [BANIN, Paragraphs 0358-0359, The detection circuit 108 is configured generate a trigger signal when no data is identified to be in the first data or the second data. The detection circuit 108 may be coupled to the demodulation circuit 106 or, as illustrated in FIG. 1, to the processing circuit 104.].
As per claim 7, CHRYSOS and BANIN teach all the limitations of claim 1 above, where BANIN teaches, an IC, wherein the network connecting the source gasket to the destination gasket includes a read address channel and a read data channel, wherein the data low trigger signal is communicated over the read data channel and the space high qualifier signal is communicated over the read address channel [BANIN, Paragraphs 0358-0359; 0368 ,To the contrary, and arbitrary number of time periods may be read from the memory to generate the data signal and the absence of payload data so that the data signal may comprise subsequent complementary signal edges separated by time periods varying according to the sequence of time periods read from the memory.].
As per claim 8, CHRYSOS and BANIN teach all the limitations of claim 7 above, where BANIN teaches, an IC, wherein the network connecting the source gasket to the destination gasket further includes a write address channel, a write data channel, and a write response channel [BANIN, Paragraphs 2267-2268, …, if a gasket circuit receives a command from the PCIe controller to change to a specific power state according to the PCIe protocol, the gasket circuit may select a power state (power mode, mode of operation) of the STEP protocol according to a predefined mapping scheme and control the STEP physical layer circuitry to change to the selected power state (power mode, mode of operation) of the STEP protocol.], wherein the space low trigger signal is communicated over the write response channel and the data high qualifier signal is communicated over the write data channel [BANIN, Paragraphs 0358-0359; 0368 ,To the contrary, and arbitrary number of time periods may be read from the memory to generate the data signal and the absence of payload data so that the data signal may comprise subsequent complementary signal edges separated by time periods varying according to the sequence of time periods read from the memory.].
As per claim 9, CHRYSOS and BANIN teach all the limitations of claim 1 above, where BANIN teaches, an IC, wherein in the push mode the source gasket serves as a master and the destination gasket serves as a slave, and in the pull mode the source gasket serves as the slave and the destination gasket serves as the master [BANIN, Paragraphs 2267-2268, …, if a gasket circuit receives a command from the PCIe controller to change to a specific power state according to the PCIe protocol, the gasket circuit may select a power state (power mode, mode of operation) of the STEP protocol according to a predefined mapping scheme and control the STEP physical layer circuitry to change to the selected power state (power mode, mode of operation) of the STEP protocol.].
As per claim 10, CHRYSOS and BANIN teach all the limitations of claim 1 above, where BANIN teaches, an IC, wherein in the push mode write data flows over a data write channel of the network from the output memory of the source gasket to the input memory of the destination gasket [BANIN, Paragraphs 2267-2268,…, if a gasket circuit receives a command from the PCIe controller to change to a specific power state according to the PCIe protocol, the gasket circuit may select a power state (power mode , mode of operation) of the STEP protocol according to a predefined mapping scheme and control the STEP physical layer circuitry to change to the selected power state (power mode, mode of operation) of the STEP protocol.].
As per claim 11, CHRYSOS and BANIN teach all the limitations of claim 1 above, where CHRYSOS teaches, an IC, wherein in the pull mode read data flows through the network over a data read channel from the output memory of the source gasket to the input memory of the destination gasket [CHRYSOS, Paragraph 0160, At step 2, a processing element (e.g., on a flow control path network) or other circuit outputs a zero to control input (e.g., multiplexer control signal) of pick node 404 (e.g., to source a one from port “0” to its output) and outputs a zero to control input (e.g., multiplexer control signal) of switch node 406 (e.g., to provide its input out of port “0” to a destination (e.g., a downstream processing element).].
As per claim 12, CHRYSOS and BANIN teach all the limitations of claim 1 above, where BANIN teaches, an IC, wherein the output memory of the source gasket is a first circular buffer, and the input memory of the destination gasket is a second circular buffer [BANIN, Paragraphs 2267-2268,…, if a gasket circuit receives a command from the PCIe controller to change to a specific power state according to the PCIe protocol, the gasket circuit may select a power state (power mode , mode of operation) of the STEP protocol according to a predefined mapping scheme and control the STEP physical layer circuitry to change to the selected power state (power mode, mode of operation) of the STEP protocol.].
As per claim 13, CHRYSOS and BANIN teach all the limitations of claim 1 above, where CHRYSOS teaches, an IC, wherein the first circuit block comprises a digital signal processor, a central processing unit, a neural processing unit, a reconfigurable compute unit, or an analog-to-digital converter (ADC) [CHRYSOS, Paragraph 0214,… FIG. 3.3C illustrates a zoomed in view of a data path 3.3C02 formed by setting a configuration value (e.g., bits) in a configuration storage (e.g., register) 3.3C06 of a circuit switched network between a first processing element 3.3C01 and a second processing element 3.3C03 according to embodiments of the disclosure.].
As per claim 14, CHRYSOS and BANIN teach all the limitations of claim 13 above, where CHRYSOS teaches, an IC, wherein the second circuit block comprises a digital signal processor, a central processing unit, a neural processing unit, a reconfigurable compute unit, or a digital-to-analog converter (DAC) [CHRYSOS, Paragraph 0214,… FIG. 3.3C illustrates a zoomed in view of a data path 3.3C02 formed by setting a configuration value (e.g., bits) in a configuration storage (e.g., register) 3.3C06 of a circuit switched network between a first processing element 3.3C01 and a second processing element 3.3C03 according to embodiments of the disclosure.].
As per claims 15-20, claims 15-20 are rejected in accordance to the same rational and reasoning as the above claims 1-14 above, wherein claims 15-20 are the method claims for the device of claims 1-14.
Conclusion
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
Escamilla et al. (US Patent Application Pub. No: 20210011533 A1) teaches an information handling system includes a baseboard management controller (BMC) and a cooling module that receives a control signal from the BMC. Escamilla discloses the cooling module includes an air mover assembly, and a foam gasket that is disposed in between the air mover assembly and the bulkhead; and a cam assembly has a cam lever holder that draws in a compression bracket to provide axial stress to the air mover assembly, a bulkhead, and the foam gasket.
WU et al.(US Patent Application Pub. No: 20210117600 A1) teaches a disclosed circuit prototyping system includes a hardware interface module configured for electronically connecting to a physical electronic device, a virtual circuit design interface to construct a virtual circuit for a plurality of virtual circuit devices including a virtual counterpart of the physical electronic device, and a circuit simulator configured to simulate the virtual circuit including communicating data with the physical electronic device by way of communication with the hardware interface module.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GETENTE A YIMER whose telephone number is (571)270-7106. The examiner can normally be reached Monday-Friday 6:30-3:00.Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached on 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GETENTE A YIMER/Primary Examiner, Art Unit 2181