Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on November 19,2024.
2. Claims 1-20 are pending and has been examined.
Information Disclosure Statement
3.The information disclosure statement (IDS) submitted on 03/24/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
4. The drawings submitted on 11/19/2024 are acceptable.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 8-15,17 and 20 are rejected under 35 U.S.C. 102(a)(1) (a)(1) as being anticipated by You “20190107853”.
In regarding to claim 1, You discloses a power supply circuit (Fig.1-5): multiphase voltage regulator) comprising: a common output node (Vout , Cout);
a first switched-mode power supply (SMPS) circuit (Fig.1: phase 1) including an output coupled to the common output node (Vout , Cout);
one or more first sensors coupled to the first SMPS circuit (The current balance circuitry 114 can include any standard circuitry for sensing and/or measuring the phase currents and the output voltage Vout of the system, see prag.0022);
a second SMPS circuit (Fig.1: phase 2) including an output coupled to the common output node (Vout , Cout);
one or more second sensors coupled to the second SMPS circuit (The current balance circuitry 114 can include any standard circuitry for sensing and/or measuring the phase currents and the output voltage Vout of the system, see prag.0022) ; and
a control circuit (controller 102) configured to:
receive, from the one or more first sensors, a first indication of a first current or a first temperature associated with the first SMPS circuit (see parag.0022);
receive, from the one or more second sensors, a second indication of a second current or a second temperature associated with the second SMPS circuit (see parag.0022);
and
control (102) , based on the first indication and the second indication, adjustment of an operating frequency of the first SMPS circuit (see parag. 0022-0023).
In regarding to claim 2, You discloses (Figs. 1-5) wherein to control adjustment of the operating frequency (see parag.0022-0024) of the first SMPS circuit (phase 1) , the control circuit (102) is configured to control decreasing the operating frequency of the first SMPS circuit when the first current or the first temperature associated with the first SMPS circuit is higher than the second current or the second temperature associated with the second SMPS circuit, respectively, until a difference between the second current or the second temperature and the first current or the first temperature, respectively, is less than a first threshold (see pararg. 0023).
In regarding to claim 4, You discloses (Figs. 1-5) wherein to control adjustment (102) of the operating frequency of the first SMPS circuit (phase 1), the control circuit (102) is configured to control increasing the operating frequency of the first SMPS circuit (phase 1) when the first current or the first temperature associated with the first SMPS circuit is lower than the second current or the second temperature associated with the second SMPS circuit, respectively, until a difference between the first current or the first temperature and the second current or the second temperature, respectively, is less than a first threshold (see parag.0023).
In regarding to claim 8, You discloses (Figs. 1-7) wherein the first current associated with the first SMPS circuit (phase 1, see parag.0022) is a first output current through the output of the first SMPS circuit (Vout, Cout)and wherein the second current associated with the second SMPS circuit (phase 2, see parag. 0022) is a second output current through the output of the second SMPS circuit (Vout , Cout. Furthermore, see parg.0022-0023).
In regarding to claim 9, You discloses (Figs. 1-7) wherein the first current associated with the first SMPS circuit is a first input current (current thru HS of phase 1) through an input of the first SMPS circuit (Vin of phase 1) and wherein the second current (current thru HS of phase 2) associated with the second SMPS circuit (phase 2) is a second input current through an input of the second SMPS circuit (Vin of phase 2).
In regarding to claim 10, You discloses (Figs. 1-7) wherein the first SMPS circuit is disposed on a first integrated circuit and wherein the second SMPS circuit is disposed on a second integrated circuit different from the first integrated circuit (plurality of phases (power stages) 100 are configured as independently package equivalent to integrated circuit, see parag.0017. Furthermore, examiner noted that an IC is known in the art )
In regarding to claim 11, You discloses (Figs. 1-7) wherein the control circuit is disposed on the first integrated circuit( VR controller 102 is configured separately as an independently package equivalent to integrated circuit, see parag.0017. Furthermore, examiner noted that an IC is known in the art )
In regarding to claim 12, You discloses (Figs. 1-7) wherein the control circuit is configured to control adjustment of the operating frequency of the first SMPS circuit incrementally over a period of time ( see parag. 0020-0024).
In regarding to claim 13, You discloses (Figs. 1-7) further comprising: a third SMPS circuit (phase 30 including an output coupled to the common output node (Vout, Cout) ; and one or more third sensors coupled to the third SMPS circuit (see parag.0022) , wherein the control circuit (102) is further configured to: receive, from the one or more third sensors (see parag.0022), a third indication of a third current or a third temperature associated with the third SMPS circuit; and control adjustment of an operating frequency of the third SMPS circuit based on the second indication and the third indication (see parag. 0022-0023).
In regarding to claim 14 , You discloses method of supplying power (Fig.1-5):, the method comprising: receiving, from one or more first sensors (see parag. 0022) coupled to a first switched-mode power supply (SMPS) circuit (phase 1) including an output coupled to a common output node (Vout, Cout), a first indication of a first current or a first temperature associated with the first SMPS circuit (see parag.0022); receiving, from one or more second sensors (see parag.0022) coupled to a second SMPS circuit (phase 2) including an output coupled to the common output node (Vout, Cout) , a second indication of a second current (see parag. 0022) or a second temperature associated with the second SMPS circuit (phase 2) ; and controlling (102) , based on the first indication and the second indication, adjustment of an operating frequency of the first SMPS circuit (see parag.0022-0023).
In regarding to claim 15, You discloses (Figs. 1-5) wherein controlling the adjustment of the operating frequency comprises decreasing the operating frequency (see parg.0022-0024) of the first SMPS circuit (phase 10 when the first current or the first temperature associated with the first SMPS circuit is higher than the second current or the second temperature associated with the second SMPS circuit (phase 2) , respectively, until a difference between the second current or the second temperature and the first current or the first temperature, respectively, is less than a first threshold (see pararg. 0023)..
In regarding to claim 17, You discloses (Figs. 1-5), wherein controlling the adjustment of the operating frequency (see prag.0022-0024) comprises increasing the operating frequency of the first SMPS circuit (phase 1) when the first current or the first temperature associated with the first SMPS circuit is lower than the second current or the second temperature associated with the second SMPS circuit, respectively, until a difference between the first current or the first temperature and the second current or the second temperature, respectively, is less than a first threshold (see parag.0023)..
In regarding to claim 20, You discloses (Figs. 1-7) wherein the first current associated with the first SMPS circuit is a first input current (current thru HS of phase 1) through an input of the first SMPS circuit (Vin of phase 1) and wherein the second current (current thru HS of phase 2) associated with the second SMPS circuit (phase 2) is a second input current through an input of the second SMPS circuit (Vin of phase 2).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over You “20190107853” in a view of Yen “11502599”.
In regarding to a combination of claims 6 and 19, You discloses (Figs. 1-5) wherein the first SMPS circuit (Fig. 1: phase 1) and the second SMPS (phase 2) but fail to discloses comprises a first charge pump circuit and wherein the second SMPS circuit comprises a second charge pump circuit.
Whereas , Yen discloses (Fig.3 : four different drivers 308A, 310A, 312A, and 314A of the “A” branch 316, and the four different drivers 308B, 310B, 312B, and 314B on the “B” branch 318 in the multi-phase SMPS circuit may include a charge pump, abstract and see col. 9, lines 65-67 and col. 10, lines 1-5).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified the multiphase voltage regulator of You to include a first and second charge pump as taught by Yen in order to minimize (or at least reduce) the cost and the layout area, thus it is less cheap and easy and easy access for maintenance .
Allowable Subject Matter
7. Claims 3,5,7, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 3 is objected because the prior art of record fails to disclose or suggest the power supply circuit including the limitation of “the control circuit is configured to control decreasing the operating frequency of the first SMPS circuit dependent on the first current or the first temperature being higher than a second threshold.”
Claim 5 is objected because the prior art of record fails to disclose or suggest the power supply circuit including the limitation of “wherein the control circuit is configured to control increasing the operating frequency of the first SMPS circuit dependent on the first current or the first temperature being lower than a second threshold.”
Claim 7 is objected because the prior art of record fails to disclose or suggest the power supply circuit including the limitation of “wherein the one or more first sensors comprise a first current sensor including a first resistive element coupled between the output of the first SMPS circuit and the common output node and wherein the one or more second sensors comprise a second current sensor including a second resistive element coupled between the output of the second SMPS circuit and the common output node.”
Claim 16 is objected because the prior art of record fails to disclose or suggest the method including the limitation of “ wherein decreasing the operating frequency depends on the first current or the first temperature being higher than a second threshold. ”
Claim 18 is objected because the prior art of record fails to disclose or suggest the method including the limitation of “ wherein increasing the operating frequency depends on the first current or the first temperature being lower than a second threshold.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhao “12283883” the present application belongs to the field of switching power supply, and particularly relates to a series-parallel switched capacitor voltage converter.
Wu “12237772” the present invention relates to electronic circuits, and more particularly to power converter circuits, including DC-DC power converter circuits.
Wagh “11671058” the present application relates to amplifiers. In particular the present application relates to gate biasing for amplifiers comprising stacked transistors which can operate in an active mode during periods of RF signal transmission, and in a standby mode during periods of non-transmission. Issues and solutions related to switching from operation in the standby mode to operation in the active mode are presented.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
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