DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 19 November 2024.
Claims 1-20 are pending and have been presented for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 1 is objected to because of the following informalities:
The following limitation appears to contain some grammar errors “… wherein the first chip is configured to perform store the second data received from the third chip into the second buffer memory, and in parallel with a first operation of storing the first data received from the second chip into the first buffer memory, a second operation of transmitting and receiving a signal relating to the second chip to and from the host.”
The Examiner recommends the following amendments to the limitation “… wherein the first chip is configured to perform storing the second data received from the third chip into the second buffer memory, and in parallel with a first operation of storing the first data received from the second chip into the first buffer memory, perform a second operation of transmitting and receiving a signal relating to the second chip to and from the host.”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 and 11-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 and 14-20 of U.S. Patent No. 12,175,120. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of the ‘120 patent as shown below.
Claims 10 and 20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 11 of U.S. Patent No. 12,175,120 in view of OTANI (U.S. Patent Application Publication #2003/0071293).
Claims 1 and 11 disclose the semiconductor device which includes a first, second and third chip. Claims 10 and 20 of the instant application contain additional limitations regarding the first, second and third chip that are not disclosed by the ‘120 patent. The ‘120 patent fails to disclose the first, second and third chip being sealed with a mold resin.
OTANI discloses performing a resin encapsulation process on a semiconductor memory device (see [0097]). The result of the resin encapsulation process is a semiconductor memory device that can exhibit stabler characteristics against any external environment (see [0098]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify the ‘120 patent to seal the first, second and third chip with a mold resin, as disclosed by OTANI. One of ordinary skill in the art would have been motivated to make such a modification to protect the semiconductor memory device from an external environment, as taught by OTANI.
12,175,120
18/952,746
1. A semiconductor device comprising:
(A) a first chip electrically connected to a terminal to which a signal from a host is input, the first chip including a first buffer memory and a second buffer memory;
(B) a second chip to which the first chip is electrically connected, the second chip including a plurality of memory cells; and
(C) a third chip to which the first chip is electrically connected in parallel with the second chip, the third chip including a plurality of memory cells;
(D) wherein the first chip is configured to: receive a first request from the host, issue a first command to the second chip after receiving the first request, receive a second request from the host after receiving the first request, and issue a second command to the third chip after receiving the second request,
(E) the second chip is configured to: read first data after receiving the first command and transmit the read first data to the first chip,
(F) the third chip is configured to: read second data after receiving the second command; and transmit the read second data to the first chip,
(G) and wherein the first chip is configured to, while storing the second data received from the third chip into the second buffer memory, perform, in parallel with a first operation of storing the first data received from the second chip into the first buffer memory, a second operation of transmitting a part of the first data from the first buffer memory to the host.
2. The semiconductor device according to claim 1,
(H) wherein the first chip is configured to perform, in parallel with the first operation of storing the first data received from the second chip into the first buffer memory, a third operation of transmitting and receiving a signal relating to the second chip to and from the host.
Claim 1. A semiconductor device comprising:
(A) a first chip electrically connected to a terminal to which a signal from a host is input, the first chip including a first buffer memory and a second buffer memory;
(B) a second chip to which the first chip is electrically connected, the second chip including a plurality of memory cells; and (C) a third chip to which the first chip is electrically connected in parallel with the second chip, the third chip including a plurality of memory cells;
(D) wherein the first chip is configured to: receive a first request from the host, issue a first command to the second chip after receiving the first request, receive a second request from the host after receiving the first request, and issue a second command to the third chip after receiving the second request,
(E) the second chip is configured to: read first data after receiving the first command and transmit the read first data to the first chip,
(F) and the third chip is configured to: read second data after receiving the second command; and transmit the read second data to the first chip,
(G) and wherein the first chip is configured to perform store the second data received from the third chip into the second buffer memory,
(H) and in parallel with a first operation of storing the first data received from the second chip into the first buffer memory, a second operation of transmitting and receiving a signal relating to the second chip to and from the host.
Claims 3/4/5/6/7/8/9/10
Claims 2/3/4/5/6/7/8/9
11. A storage system comprising;
(A) the semiconductor device according to claim 1;
(B) a host;
(C) and a communication path that is connected to the semiconductor device and the host.
Claim 11. A storage system comprising:
(A) the semiconductor device according to claim 1;
(B) a host;
(C) and a communication path that is connected to the semiconductor device and the host.
Claims 12/14/15/16/17/18/19/20
Claims 12/13/14/15/16/17/18/19
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5-9, 11, 13 and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI (U.S. Patent Application Publication #2019/0095134) in view of LEE-404 (U.S. Patent Application Publication #2014/0226404) and SASSA (U.S. Patent #6,345,333).
Claim 1. LI discloses A semiconductor device comprising: a first chip electrically connected to a terminal to which a signal from a host is input (see [0056], [0058]: controller can received read and write requests from a host), the first chip including a first buffer memory and a second buffer memory (see [0052]-[0053]: integrated accumulation buffer, each segment of the buffer corresponds to a channel, the segments would be the first and second buffer memory); a second chip to which the first chip is electrically connected, the second chip including a plurality of memory cells (see [0049]: controller is connected to multiple flash dies in parallel, the flash die would be the second/third chip); and a third chip to which the first chip is electrically connected in parallel with the second chip, the third chip including a plurality of memory cells (see [0049]: controller is connected to multiple flash dies in parallel, the flash die would be the second/third chip); wherein the first chip is configured to: receive a first request from the host (see [0056]; read command from a host), issue a first command to the second chip after receiving the first request (see [0056]: controller obtains a page from memory in response to a read request from a host, the chip that is accessed would depend on the data address), receive a second request from the host after receiving the first request (see [0056]: host can issue multiple read requests during operation of the system), and issue a second command to the third chip after receiving the second request (see [0056]: controller obtains a page from memory in response to a read request from a host, the chip that is accessed would depend on the data address), the second chip is configured to: read first data after receiving the first command and transmit the read first data to the first chip (see [0056]: data is transmitted from the page buffer in the chip to the controller), and the third chip is configured to: read second data after receiving the second command; and transmit the read second data to the first chip (see [0056]: data is transmitted from the page buffer in the chip to the controller), and wherein the first chip is configured to perform store the second data received from the third chip into the second buffer memory (see [0056]: controller stores data received from the flash memory chip into buffer 252), and in parallel with (see LEE-404 and SASSA below) a first operation of storing the first data received from the second chip into the first buffer memory (see [0056]: controller stores data received from the flash memory chip into buffer 252), a second operation of transmitting and receiving a signal relating to the second chip to and from the host (see LEE-404 and SASSA below).
LEE-404 discloses the following limitations that are not disclosed by LI: in parallel with a first operation of storing the first data received from the second chip into the first buffer memory a second operation of transmitting and receiving a signal relating to the second chip to and from the host (see [0033]: busy signal is transmitted to a host while executing a read or write operation on the flash memory). The claimed first operation is referring to a read operating where data is transferred from the memory chip to the controller. LEE-404 discloses that while a read is being performed, a busy signal is transmitted to the host. The busy signal is considered a signal relating to the second chip. The busy signal is related in that the signal conveys the status of the chip. LEE-404 discloses that the busy signal is sent while a read/write is performed, and this is considered as being performed in parallel. Sending a busy (or ready) signal to the host allows the host to determine the state of the memory system (see SASSA column 5, lines 5-10).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to perform a first operation in parallel with transmitting/sending a signal to the host, as disclosed by LEE-404. One of ordinary skill in the art would have been motivated to make such a modification to allow the host to recognize the operation state of the memory system, as taught by SASSA. LI, LEE-404 and SASSA are analogous/in the same field of endeavor as both references are directed to managing communication with a memory system.
Claim 3. The semiconductor device according to claim 1, wherein the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal relating to the third chip to and from the host (see LEE-404 [0033]: busy signal is transmitted to a host while executing a read or write operation on the flash memory).
Claim 5. The semiconductor device according to claim 1, wherein the first chip is configured to supply a first signal to the second chip based on the issuance of the first command (see LI [0056]: controller obtaining data from the flash die involves sending a signal to activate the memory and complete the data transfer), and the second chip is configured to read the first data based on the first command and the first signal and transmit the read first data to the first chip (see LI [0056]: data is transferred from the page buffer on the flash die to the controller).
Claim 6. The semiconductor device according to claim 1, further comprising: a first channel that electrically connects the first chip and the second chip; and a second channel that electrically connects the first chip and the third chip (see LI [0049]: channel for each flash die).
Claim 7. The semiconductor device according to claim 6, wherein the first chip is configured to control the first channel independently of the host in response to a request for the second chip received from the host, and the first chip is configured to control the second channel independently of the host in response to a request for the third chip received from the host (see LI [0056]: host sends a read request to the controller, then the controller performs another operation to fetch the data from the die, the host does not know which die the data is stored in, the controller is therefore considered to be controlling the channels independently from the host request).
Claim 8. The semiconductor device according to claim 7, wherein the request for the second chip is a data output request with respect to the second chip, and the request for the third chip is a data output request with respect to the third chip (see LI [0056]: a read request is a data output request).
Claim 9. The semiconductor device according to claim 1, wherein each of the second chip and the third chip includes a NAND-type flash memory chip (see LI [0049]: NAND dies).
Claim 11. LI discloses A storage system comprising: the semiconductor device according to claim 1 (see rejection of claim 1 above); a host (see figure 1A, server 116); and a communication path that is connected to the semiconductor device and the host (see figure 1A elements 116, 142, 140 – communication between the server and the SSD through the controller).
Claim 13. The storage system according to claim 11, wherein in the semiconductor device, the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal relating to the third chip to and from the host (see LEE-404 [0033]: busy signal is transmitted to a host while executing a read or write operation on the flash memory).
Claim 15. The storage system according to claim 11, wherein in the semiconductor device, the first chip is configured to supply a first signal to the second chip based on the issuance of the first command (see LI [0056]: controller obtaining data from the flash die involves sending a signal to activate the memory and complete the data transfer), and the second chip is configured to read the first data based on the first command and the first signal and transmit the read first data to the first chip (see LI [0056]: data is transferred from the page buffer on the flash die to the controller).
Claim 16. The storage system according to claim 11, wherein the semiconductor device further comprises: a first channel that electrically connects the first chip and the second chip; and a second channel that electrically connects the first chip and the third chip (see LI [0049]: channel for each flash die).
Claim 17. The storage system according to claim 16, wherein in the semiconductor device, the first chip is configured to control the first channel independently of the host in response to a request for the second chip received from the host, and the first chip is configured to control the second channel independently of the host in response to a request for the third chip received from the host (see LI [0056]: host sends a read request to the controller, then the controller performs another operation to fetch the data from the die, the host does not know which die the data is stored in, the controller is therefore considered to be controlling the channels independently from the host request).
Claim 18. The storage system according to claim 17, wherein in the semiconductor device, the request for the second chip is a data output request with respect to the second chip, and the request for the third chip is a data output request with respect to the third chip (see LI [0056]: a read request is a data output request).
Claim 19. The storage system according to claim 11, wherein in the semiconductor device, each of the second chip and the third chip includes a NAND-type flash memory chip (see LI [0049]: NAND dies).
Claim(s) 2, 4, 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI (U.S. Patent Application Publication #2019/0095134), LEE-404 (U.S. Patent Application Publication #2014/0226404) and SASSA (U.S. Patent #6,345,333) as applied to claims 1, 3, 5-9, 11, 13 and 15-19 above, and further in view of LEE-932 (U.S. Patent Application Publication #2019/0212932) and OKITA (U.S. Patent Application Publication #2018/0196768).
Claim 2. The semiconductor device according to claim 1 (see LI above), wherein the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal to and from the second chip (see LEE-932 and OKITA below).
LEE-932 discloses the following limitations that are not disclosed by LI: wherein the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal to and from the second chip (see [0056]-[0057]: each memory channel can operate independently from each other). LI already discloses a memory system that includes multiple memory channels. LI also discloses the first operation, discussed above in the rejection of claim 1. Furthermore, LI issuing a command to the second chip, such as a read or write, would be considered a third operation. While LI discloses performing both operations, LI does not disclose the operations are performed in parallel. LEE-932 discloses the ability to allow for parallel access to each channel. Fetching data from multiple channels in parallel improves sequential read performance (see OKITA [0101]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to perform a first operation and a third operation in parallel, as disclosed by LEE-932. One of ordinary skill in the art would have been motivated to make such a modification to improve sequential read performance, as taught by OKITA. LI, LEE-932 and OKITA are analogous/in the same field of endeavor as both references are directed to accessing multiple channel flash memory systems.
Claim 4. The semiconductor device according to claim 1 (see LI above), wherein the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal to and from the third chip (see LEE-932 and OKITA below).
LEE-932 discloses the following limitations that are not disclosed by LI: wherein the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal to and from the third chip (see [0056]-[0057]: each memory channel can operate independently from each other). LI already discloses a memory system that includes multiple memory channels. LI also discloses the first operation, discussed above in the rejection of claim 1. Furthermore, LI issuing a command to the third chip, such as a read or write, would be considered a third operation. While LI discloses performing both operations, LI does not disclose the operations are performed in parallel. LEE-932 discloses the ability to allow for parallel access to each channel. Fetching data from multiple channels in parallel improves sequential read performance (see OKITA [0101]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to perform a first operation and a third operation in parallel, as disclosed by LEE-932. One of ordinary skill in the art would have been motivated to make such a modification to improve sequential read performance, as taught by OKITA. LI, LEE-932 and OKITA are analogous/in the same field of endeavor as both references are directed to accessing multiple channel flash memory systems.
Claim 12. The storage system according to claim 11 (see LI above), wherein in the semiconductor device, the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal to and from the second chip (see LEE-932 and OKITA below).
LEE-932 discloses the following limitations that are not disclosed by LI: wherein the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal to and from the second chip (see [0056]-[0057]: each memory channel can operate independently from each other). LI already discloses a memory system that includes multiple memory channels. LI also discloses the first operation, discussed above in the rejection of claim 1. Furthermore, LI issuing a command to the second chip, such as a read or write, would be considered a third operation. While LI discloses performing both operations, LI does not disclose the operations are performed in parallel. LEE-932 discloses the ability to allow for parallel access to each channel. Fetching data from multiple channels in parallel improves sequential read performance (see OKITA [0101]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to perform a first operation and a third operation in parallel, as disclosed by LEE-932. One of ordinary skill in the art would have been motivated to make such a modification to improve sequential read performance, as taught by OKITA. LI, LEE-932 and OKITA are analogous/in the same field of endeavor as both references are directed to accessing multiple channel flash memory systems.
Claim 14. The storage system according to claim 11 (see LI above), wherein in the semiconductor device, the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal to and from the third chip (see LEE-932 and OKITA below).
LEE-932 discloses the following limitations that are not disclosed by LI: wherein the first chip is configured to perform, in parallel with the first operation, a third operation of transmitting and receiving a signal to and from the third chip (see [0056]-[0057]: each memory channel can operate independently from each other). LI already discloses a memory system that includes multiple memory channels. LI also discloses the first operation, discussed above in the rejection of claim 1. Furthermore, LI issuing a command to the third chip, such as a read or write, would be considered a third operation. While LI discloses performing both operations, LI does not disclose the operations are performed in parallel. LEE-932 discloses the ability to allow for parallel access to each channel. Fetching data from multiple channels in parallel improves sequential read performance (see OKITA [0101]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to perform a first operation and a third operation in parallel, as disclosed by LEE-932. One of ordinary skill in the art would have been motivated to make such a modification to improve sequential read performance, as taught by OKITA. LI, LEE-932 and OKITA are analogous/in the same field of endeavor as both references are directed to accessing multiple channel flash memory systems.
Claim(s) 10 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI (U.S. Patent Application Publication #2019/0095134), LEE-404 (U.S. Patent Application Publication #2014/0226404) and SASSA (U.S. Patent #6,345,333) as applied to claims 1, 3, 5-9, 11, 13 and 15-19 above, and further in view of OTANI (U.S. Patent Application Publication #2003/0071293).
Claim 10. The semiconductor device according to claim 1 (see LI above), wherein the first chip, the second chip and the third chip are sealed with a mold resin (see OTANI below).
OTANI discloses the following limitations that are not disclosed by LI: herein the first chip, the second chip and the third chip are sealed with a mold resin (see [0097]). The result of the resin encapsulation process is a semiconductor memory device that can exhibit stabler characteristics against any external environment (see [0098]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to seal the first, second and third chip with a mold resin, as disclosed by OTANI. One of ordinary skill in the art would have been motivated to make such a modification to protect the semiconductor memory device from an external environment, as taught by OTANI. LI and OTANI are analogous/in the same field of endeavor as both references are directed to systems that include memory devices.
Claim 20. The storage system according to claim 11 (see LI above), wherein in the semiconductor device, the first chip, the second chip and the third chip are sealed with a mold resin (see OTANI below).
OTANI discloses the following limitations that are not disclosed by LI: herein the first chip, the second chip and the third chip are sealed with a mold resin (see [0097]). The result of the resin encapsulation process is a semiconductor memory device that can exhibit stabler characteristics against any external environment (see [0098]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LI to seal the first, second and third chip with a mold resin, as disclosed by OTANI. One of ordinary skill in the art would have been motivated to make such a modification to protect the semiconductor memory device from an external environment, as taught by OTANI. LI and OTANI are analogous/in the same field of endeavor as both references are directed to systems that include memory devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2136