DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The Information Disclosure Statement filed on 5 May 2026 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, 11, and 20 is/are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Ramanathan et al. (Pub. No. US 2024/0069965).
Claim 1:
Ramanathan et al. disclose a system, comprising:
a host configured to send an execute program command, wherein the execute program command indicates one or multiple programs and an order of executing the multiple programs when the multiple programs are indicated [pars. 0030-0041 – Host forwards an execution pipeline indicating one or more compute functions to a computational storage device. (“A host computing device may forward the execution pipeline to the CSD as an input. The CSD may execute the compute functions in the order indicated in the execution pipeline.”)]; and
a computational storage device configured to:
receive the execute program command from the host [pars. 0030-0041 – The computational storage device receives the execution task from the host. (“In some embodiments, the CSD includes a pipeline manager (referred to as an arbiter) that receives a task including the compute functions to be executed, as input from an application running on the host. The arbiter may manage execution of the compute functions according to the order indicated in the task.”)]; and
in response to determining that the execute program command indicates multiple programs, execute the multiple programs according to the order of executing the multiple programs [pars. 0030-0041 – The compute functions are executed in the order indicated in the task. (“In some embodiments, the CSD includes a pipeline manager (referred to as an arbiter) that receives a task including the compute functions to be executed, as input from an application running on the host. The arbiter may manage execution of the compute functions according to the order indicated in the task.”)],
wherein the order of executing the multiple programs is indicated by a mapping table comprised in the execute program command or stored in a data buffer [pars. 0030-0041 – Host forwards an execution pipeline indicating one or more compute functions to a computational storage device. The order is indicated by the execution pipeline. (“A host computing device may forward the execution pipeline to the CSD as an input. The CSD may execute the compute functions in the order indicated in the execution pipeline.”)].
Claim 7 (as applied to claim 1 above):
Ramanathan et al. disclose,
wherein the order of executing the multiple programs is sequential [par. 0041 – “The task may include one or more compute functions that may be executed according to one order by one application (e.g., application 112a), and according to a different order in another application (e.g., application 112b or application 112c).”].
Claim 11:
Ramanathan et al. disclose a method, comprising:
receiving and parsing an execute program command from a host, wherein the execute program command indicates one or multiple programs to be executed by a computational storage device and an order of executing the multiple programs when the multiple programs are indicated [pars. 0030-0041 – The computational storage device receives the execution task from the host. (“In some embodiments, the CSD includes a pipeline manager (referred to as an arbiter) that receives a task including the compute functions to be executed, as input from an application running on the host. The arbiter may manage execution of the compute functions according to the order indicated in the task.”)]; and
in response to determining that the execute program command indicates multiple programs, executing the multiple programs according to the order of executing the multiple programs [pars. 0030-0041 – The compute functions are executed in the order indicated in the task. (“In some embodiments, the CSD includes a pipeline manager (referred to as an arbiter) that receives a task including the compute functions to be executed, as input from an application running on the host. The arbiter may manage execution of the compute functions according to the order indicated in the task.”)],
wherein the order of executing the multiple programs is indicated by a mapping table comprised in the execute program command or stored in a data buffer [pars. 0030-0041 – Host forwards an execution pipeline indicating one or more compute functions to a computational storage device. The order is indicated by the execution pipeline. (“A host computing device may forward the execution pipeline to the CSD as an input. The CSD may execute the compute functions in the order indicated in the execution pipeline.”)].
Claim 20:
Ramanathan et al. disclose a computational storage device, comprising:
computational resources [fig. 2; pars. 0046-0052 – compute kernels (“In some embodiments, the arbiter 200 receives an input or task 204a, 204b (collectively referenced as 204) from an application 112, and manages execution of the compute functions identified in the task, in the order that is identified in the task. The arbiter 200 may further manage the storage memory 120 and communication with the compute kernels for executing compute functions.”)]; and
a controller coupled to the computational resources and configured to control the computational resources [fig. 2; pars. 0046-0052 – arbiter (“In some embodiments, the arbiter 200 receives an input or task 204a, 204b (collectively referenced as 204) from an application 112, and manages execution of the compute functions identified in the task, in the order that is identified in the task. The arbiter 200 may further manage the storage memory 120 and communication with the compute kernels for executing compute functions.”)],
wherein controller is configured to:
receive and parse an execute program command from a host, wherein the execute program command indicates one or multiple programs and an order of executing the multiple programs when the multiple programs are indicated [pars. 0030-0041 – The computational storage device receives the execution task from the host. (“In some embodiments, the CSD includes a pipeline manager (referred to as an arbiter) that receives a task including the compute functions to be executed, as input from an application running on the host. The arbiter may manage execution of the compute functions according to the order indicated in the task.”)], and
wherein the computational resources are configured to:
in response to determining that the execute program command indicates multiple programs, execute the multiple programs according to the order of executing the multiple programs [pars. 0030-0041 – The compute functions are executed in the order indicated in the task. (“In some embodiments, the CSD includes a pipeline manager (referred to as an arbiter) that receives a task including the compute functions to be executed, as input from an application running on the host. The arbiter may manage execution of the compute functions according to the order indicated in the task.”)],
wherein the order of executing the multiple programs is indicated by a mapping table comprised in the execute program command or stored in a data buffer [pars. 0030-0041 – Host forwards an execution pipeline indicating one or more compute functions to a computational storage device. The order is indicated by the execution pipeline. (“A host computing device may forward the execution pipeline to the CSD as an input. The CSD may execute the compute functions in the order indicated in the execution pipeline.”)].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramanathan et al. (Pub. No. US 2024/0069965) as applied to claims 1 and 11 above, respectively, and further in view of Khan et al. (Pub. No. US 2021/0342103).
Claim 2 (as applied to claim 1 above):
Ramanathan et al. disclose all the limitations above but do not specifically disclose,
wherein the computational storage device is further configured to send a command status to the host after completion of execution of the multiple programs, wherein the command status is a success status corresponding to the execution of the multiple programs being successful or a failed status corresponding to the execution of the multiple programs being failed, wherein the failed status comprises one or more indices corresponding to one or more of the multiple programs being failed [Ramanathan et al. disclose returning the result of the task to the host (which could be considered indicative of the command status), but do not specifically disclose sending a command status.].
In the same field of endeavor, Khan et al. disclose,
wherein the computational storage device is further configured to send a command status to the host after completion of execution of the multiple programs, wherein the command status is a success status corresponding to the execution of the multiple programs being successful or a failed status corresponding to the execution of the multiple programs being failed, wherein the failed status comprises one or more indices corresponding to one or more of the multiple programs being failed [par. 0087 – “In certain embodiments, the results of the transformations are sent from the storage device 106 to the host 101 through an NVMe completion command (or other suitable message) which indicates success or failure. In a particular embodiment, the completion command may include a pointer to a completion log that may indicate the success or failure of the different transformation results or provide other suitable information associated with the transforms (or the information may be provided within the completion command itself)”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ramanathan et al. to include completion messaging, as taught by Khan et al., in order to improve data integrity by allowing the host to make informed decisions based on the success or failure of an operation.
Claim 12 (as applied to claim 11 above):
Claim 12, directed to a method, is rejected for the same reasons set forth in the rejection of claim 2 above, mutatis mutandis.
Claim(s) 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramanathan et al. (Pub. No. US 2024/0069965) as applied to claim 1 above, and further in view of Tran et al. (Pub. No. US 2021/0342103).
Claim 21 (as applied to claim 1 above):
Ramanathan et al. disclose all the limitations above but do not specifically disclose,
wherein the order of executing the multiple programs is parallel.
In the same field of endeavor, Tran et al. disclose,
wherein the order of executing the multiple programs is parallel [par. 0005 – “In general, the PAM 24 collects the resources 6 required to execute each task 4 of a parallel job, whether the job is parallel or sequential, or a combination of both. In this way, the PAM 24 provides a point for job control. In one embodiment, the PAM 24 controls the execution of the parallel job, such as by performing the functions of stop, resume and suspension of a parallel job, or the tasks of a parallel job.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ramanathan to include parallel execution, as taught by Tran et al., in order to improve performance.
Claim 22 (as applied to claim 1 above):
Ramanathan et al. disclose all the limitations above but do not specifically disclose,
wherein the order of executing the multiple programs is a combination of sequential and parallel.
In the same field of endeavor, Tran et al. disclose,
wherein the order of executing the multiple programs is a combination of sequential and parallel [par. 0005 – “In general, the PAM 24 collects the resources 6 required to execute each task 4 of a parallel job, whether the job is parallel or sequential, or a combination of both. In this way, the PAM 24 provides a point for job control. In one embodiment, the PAM 24 controls the execution of the parallel job, such as by performing the functions of stop, resume and suspension of a parallel job, or the tasks of a parallel job.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ramanathan to include parallel execution, as taught by Tran et al., in order to improve performance.
Allowable Subject Matter
Claims 3, 5, 6, 8-10, 13, 15, 16, 18, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed February 26, 2026 have been fully considered but they are not persuasive.
Applicant argues that Ramanathan does not disclose that the order of executing the multiple programs is indicated by the mapping table.
Examiner submits that the claim language recites “wherein the order of executing the multiple programs is indicated by a mapping table comprised in the execute program command or stored in a data buffer. Ramanathan discloses that each task includes ordering information for the compute kernels to be invoked and the tasks to be run are stored in a wait queue. Examiner suggests further detailing the structural arrangement of the mapping table.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LARRY T. MACKALL
Primary Examiner
Art Unit 2131
31 May 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139
Prosecution Insights