FINAL OFFICE ACTION
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 2014/0376320 to Loh et al. (hereinafter Loh) in view of U.S. Patent No. 9,135,100 to Ware.
Loh discloses:
1. A memory, a processing unit internal to the memory being configured to:
receive a memory address associated with an error in data stored at the memory (para. [0049] and Fig. 5, block 502);
store the memory address in an entry of an index stored on the memory (paras. [0023], [0049] and Fig. 5, blocks 504-510);
store a corrected version of the data in a portion of a spare memory of the memory (paras. [0026], [0044], [0045]);
map the entry of the index to the portion of the spare memory holding the corrected version of the data (paras. [0023], [0026], [0041]); and
use the portion of the spare memory to perform a memory access associated with the data (para. [0024], [0025], [0041], [0043]).
Loh does not disclose expressly receiving the memory address from a device external to the memory.
Ware teaches receiving a memory address associated with an error from a device external to the memory (col. 2, lns. 14-32 and lns. 47-55).
Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to modify Loh by receiving the memory address from an external device, as taught by Ware. A person of ordinary skill in the art would have been motivated to do so in order to have the ability to disable error management within the memory device, especially when the error management is available in another device, as discussed by Ware (col. 2, lns. 22-27). In this manner, it would have been obvious to try error management within the memory device, and external to the memory device within another device, as discussed by Ware.
Modified Loh discloses:
2. The memory of claim 1, wherein:
the memory comprises an error correction code portion to protect against errors in the index, and the index comprises a valid indicator configured to indicate an active status of the memory address in the entry of the index (Loh - paras. [0020], [0023]).
3. The memory of claim 2, wherein the error correction code portion generates the corrected version of the data (Loh - paras. [0040]).
4. The memory of claim 1, wherein the processing unit is configured to:
search the index based on the memory access comprising a write access (Loh - paras. [0024]); and
write data of the write access to the portion of the spare memory based on a determination that the write access is associated with the memory address stored in the entry of the index (Loh - para. [0026]).
5. The memory of claim 1, wherein the processing unit is configured to:
search the index based on the memory access comprising a read access (Loh - para. [0024]); and
read data from the portion of the spare memory based on a determination that the read access is associated with the memory address stored in the entry of the index (Loh - para. [0025]).
7. The memory of claim 1, wherein the memory comprises memory dies stacked on a logic die (Loh - paras. [0018], [0051], [0052]).
8. The memory of claim 7, wherein the memory dies of the memory are interconnected by through-silicon vias (TSVs) (para. [0054]).
Claims 9-13, 15, and 16 are a method including steps identical to the steps performed by the memory of claims 1-5, 7, and 8, and are rejected under the same rationale.
Claims 17-20 are a non-transitory computer-readable medium for performing the identical steps as the memory of claims 1-5, and are rejected under the same rationale.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Loh in view of Ware and further in view of U.S. Patent Pub. No. 2014/0189282 to Gu et al. (hereinafter Gu).
Loh does not disclose expressly:
6. The memory of claim 1, wherein the processing unit is configured to:
monitor a usage level of the spare memory; and
provide an indicator of the usage level of the spare memory.
Gu teaches a storage node configured to:
monitor a usage level of the spare memory (paras. [0047], [0048], [0074] and Fig. 6, step 610); and
provide an indicator of the usage level of the spare memory (paras. [0076], [0077] - spare memory space determining unit 130 provides determined sizes).
Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to modify Loh by monitoring a usage level and providing an indicator of the usage level, as taught by Gu. A person of ordinary skill in the art would have been motivated to do so in order to minimize wear rate and latency of the memory, as well as improving performance of the storage system, as discussed by Gu (paras. [0062], [0066]). In this manner, it would have been obvious to a person of ordinary skill in the art to combine Gu with Loh to achieve the claimed invention.
Claim 14 is a method including steps identical to the steps performed by the memory of claim 6, and is rejected under the same rationale.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Philip Guyton whose telephone number is (571)272-3807. The examiner can normally be reached M-F 8:00-4:30.
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/PHILIP GUYTON/ Primary Examiner, Art Unit 2113
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