DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a1) as being anticipated by US20150220280 (ISHIBZAKI).
With respect to claim 1, ISHIZAKI teaches device, comprising: a cache processor to execute an instruction on behalf of an application (CPU 136 functions as array management unit 201, I/O controller 202, logical volume management unit 203, tier management unit 204 and cache controller 205 in accordance with program codes of storage control program loaded on local memory 134) [Par. 0046; Par. 0034-0037]
a storage medium to store the instruction, wherein the instruction is part of a cache program associated with the application (program codes of the storage control program loaded on local memory 134 with the CPU 136 to execute the storage control program, stored in local memory management function including cache control function , and wherein the device communicates with at least one of a first storage and a second storage of a storage device based at least in part on the instruction (the storage controller 13 (CPU 136) to manage the storage areas of high-speed storage 11 and low-speed storage 12 as upper and lower tiers, respectively, using the tier management function, i.e. controlling the entire tiered storage system 10) [Par. 0038; Par. 0034; Par. 0045-0048].
With respect to claim 2, ISHIZAKI teaches the device, wherein the cache processor includes: a fetch unit to fetch the instruction from the storage medium; and an execution unit to execute instruction (storage control program beforehand stored in local HDD is loaded from local HDD to control program area during activation of storage controller and at least part of the storage control program executed by CPU) [Par. 0048-0049].
With respect to claim 3, ISHIZAKI teaches the device, wherein the cache processor further includes a scheduler unit to schedule execution of the instruction by the execution unit (storage control program including functional elements executed by CPU during activation of storage controller) [Par. 0048-0049].
With respect to claim 4, ISHIZAKI teaches the device, further comprising a thread manager to manage a first thread and a second thread of the cache program executing on the cache processor (storage controller comprising array management unit functional elements being software modules realized when CPU 136 in storage controller executes the storage control program) [Par. 0048].
With respect to claim 5, ISHIZAKI teaches the device, wherein the storage medium is configured to store metadata including access information for a data stored in the first storage or the second storage or a tag for the data (data transfer between the tiers using tier management function based on physical volume management table) [Par. 0038-0039].
With respect to claim 6, ISHIZAKI teaches storage device, comprising: a first storage for a data (storage areas of high-speed storage 11 as upper); a second storage for the data (low-speed storage 12 lower tiers); a data controller to manage access to the data on the first storage and the second storage (the storage controller 13 (CPU 136) to manage the storage areas of high-speed storage 11 and low-speed storage 12 as upper and lower tiers) [Par. 0038; Par. 0034]; and a device, including: a cache processor to execute an instruction on behalf of an application (CPU 136 to function as array management unit 201, I/O controller 202, logical volume management unit 203, tier management unit 204 and cache controller 205 in accordance with program codes of storage control program loaded on local memory 134) [Par. 0046; Par. 0034-0037]; and a storage medium to store the instruction, wherein the instruction is part of a cache program associated with the application (program codes of storage control program loaded on local memory 134 with the CPU 136 to execute the storage control program, stored in local memory management function including cache control function) [Par. 0046; Par. 0034-0037], and wherein the device communicates with at least one of the first storage and the second storage of based at least in part on the instruction (the storage controller 13 (CPU 136) to manage the storage areas of high-speed storage 11 and low-speed storage 12 as upper and lower tiers, respectively, using the tier management function) [Par. 0038; Par. 0034].
With respect to claim 7, ISHIZAKI teaches the storage device, wherein: the first storage includes a first speed and a first capacity; the second storage includes a second speed and a second capacity; the first speed is faster than the second speed; and the second capacity is larger than the first capacity (first storage device including a first physical volume, and a second storage device including a second physical volume, having a lower access speed than the first storage device, and having a greater storage capacity than the first storage device) [Par. 0031-0032].
With respect to claim 8, ISHIZAKI teaches the storage device, further comprising: a first controller to manage access to the data on the first storage; and a second controller to manage access to the data on the second storage (incorporated in storage controller in a flash storage array (high-speed storage) and storage controller (CPU 136) constructed HDD array (the low-speed storage) for management function [Par. 0034-0037].
With respect to claim 9, ISHIZAKI teaches storage device featuring method, comprising: receiving, at a device, a request from an application executing on a processor to access a data stored on a storage device (program codes of storage control program loaded on local memory and executed by CPU to access data stored on storage memory) [Par. 0041-0042]; determining, by the device, whether the data is stored on a first storage or a second storage of the storage device (determining, using logical storage management characteristics , which storage device hold requested data) [Par. 0055; Par. 0071-0073] ; and using, by the device, a cache program associated with the application to manage the data on the first storage and the second storage of the storage device (program codes of storage control program loaded on local memory 134 with the CPU 136 to execute the storage control program, stored in local memory management function including cache control function) [Par. 0046; Par. 0034-0037].
With respect to claim 10, ISHIZAKI teaches storage device featuring method, wherein determining, by the device, whether the data is stored on the first storage or the second storage of the storage device (storage management table including entries used to hold information that indicates which storage area of which physical volume corresponds to a storage area in a logical volume constructed in the tiered storage system ) [Par. 0052-0053] includes: fetching, by a fetching unit of the device, an instruction of the cache program from a storage medium; and executing, by an execution unit of the device, the instruction (referring to entries volume management table that includes the searched physical volume the storage management access information to execute request in either tier storage) [[Par. 0051-0052; Par. 0103-0105].
With respect to claim 11, ISHIZAKI teaches storage device featuring method, wherein: determining, by the device, whether the data is stored on the first storage or the second storage of the storage device (storage management table including entries used to hold information that indicates which storage area of which physical volume corresponds to a storage area in a logical volume constructed in the tiered storage system ) [Par. 0052-0053] includes determining, by the device, that the data is stored on the first storage; and using, by the device, the cache program associated with the application to manage the data on the first storage and the second storage of the storage device includes updating a metadata of the data (using the storage control program loaded on local memory with the CPU to execute the storage control program managing change in storage management table and updating the change in management table) [Par. 0051-0052; Par. 0092-0094; Par. 0103-0105].
With respect to claim 12, ISHIZAKI teaches storage device featuring method, wherein using, by the device, the cache program associated with the application to manage the data on the first storage and the second storage of the storage device further includes issuing, by the device, a second request to access the data to a data controller of the storage device (managing access by searching the storage management table for an entry associated the request and further manage whether the search returns a match to designate a replication from the source) [Par. 0130-035; Par. 0106-0108].
With respect to claim 13, ISHIZAKI teaches storage device featuring method, further comprising sending, by the data controller, a response to the application executing on the processor (controller controlling data transfer from and to host in response to a request of data access and supplying a response to the data access request) [Par. 0041-0042].
With respect to claim 14, ISHIZAKI teaches storage device featuring method, wherein: determining, by the device, whether the data is stored on the first storage or the second storage of the storage device includes determining, by the device, that the data is stored on the second storage (storage management table including entries used to hold information that indicates which storage area of which physical volume corresponds to a storage area in a logical volume constructed in the tiered storage system ) [Par. 0052-0053]; and using, by the device, the cache program associated with the application to manage the data on the first storage and the second storage of the storage device includes copying, by the device, the data from the second storage to the first storage (using the storage control program loaded on local memory with the CPU to execute the storage control program managing change in storage management table and copying the data from low-speed storage to high-speed storage) [Par. 0051-0052; Par. 0130-0135; Par. 0092-0094].
With respect to claim 15, ISHIZAKI teaches storage device featuring method, wherein copying, by the device, the data from the second storage to the first storage includes: reading the data from the second storage; and writing the data to the first storage (the cache controller implementing storage synchronization processing synchronization request being a command for instructing cache controller to write (copy or reflect) dirty data (i.e., data not reflected in in a particular tiered storage) [Par. 0130-0135].
With respect to claim 16, ISHIZAKI teaches storage device featuring method, wherein reading the data from the second storage further includes receiving, by the device, the data from the data controller (the storage controller storing actual data corresponding to the dirty data, when the cache area stores the dirty data in synchronization request) [Par. 0130-0133].
With respect to claim 17, ISHIZAKI teaches storage device featuring method, wherein copying, by the device, the data from the second storage to the first storage includes evicting, by the device, a second data stored on the first storage (the storage storing actual data corresponding to the dirty data, when the cache area stores the dirty data in synchronization request issued also when dirty data must be evicted from tiered storage storing the dirty data in order to release the storage area) [Par. 0130-0133].
With respect to claim 18, ISHIZAKI teaches storage device featuring method, wherein evicting, by the device, a second data stored on the first storage includes: reading the second data from the first storage; and writing the second data to the second storage (the cache controller implementing storage synchronization processing synchronization request being a command for instructing cache controller to write (copy or reflect) dirty data (i.e., data not reflected in in a particular tiered storage) [Par. 0130-0133].
With respect to claim 19, ISHIZAKI teaches storage device featuring method, wherein: reading the second data from the first storage includes issuing, by the device, a second request to a data controller to read the second data from the first storage; and writing the second data to the second storage includes issuing, by the device, a third request to the data controller to write the second data to the second storage( the cache controller implementing storage synchronization processing synchronization request being a command for instructing cache controller to write (copy or reflect) dirty data (i.e., data not reflected in in a particular tiered storage) [Par. 0133-0135].
With respect to claim 20, ISHIZAKI teaches storage device featuring method, wherein reading the second data from the first storage further includes receiving, by the device, the second data from the data controller (the storage controller storing actual data corresponding to the dirty data, when the cache area stores the dirty data in synchronization request) [Par. 0130-0133].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
A. De, M. Gokhale, R. Gupta and S. Swanson, "Minerva: Accelerating Data Analysis in Next-Generation SSDs," 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines, Seattle, WA, USA, 2013, pp. 9-16.
US 9026765 B1 (MARSHAK et al) teaching techniques processing a data operation that writes first data to a data portion currently stored on first physical storage of a first storage tier of a data storage system, including storage tiers each having a different performance ranking relative to other storage tiers.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth LO can be reached at (571) 272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PIERRE MICHEL BATAILLE/ Primary Examiner, Art Unit 2136