DETAILED ACTION
This Office action is in response to the application filed on 20 November 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim limitations “a first input terminal of the NOR gate receives the first pulse wave or the third pulse wave,” and “, a reset terminal of the latch receives the second pulse wave or the fourth pulse wave” are conflict with corresponding drawing and specification in the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2, and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kailang Hang et. al (US20160164414A1; hereafter “Hang”).
-Regarding claim 1:
Hang discloses:
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A voltage conversion circuit, comprising: a plurality of voltage converters (Fig. 2: CH1,2,3), wherein the plurality of voltage converters are connected in parallel and jointly generate an output voltage according to a plurality of control signals (Fig. 2: Vout) respectively; a feedback circuit (paragraph 0018; “feedback loop”), coupled to the plurality of voltage converters, generating a plurality of feedback signals according to a switching voltage on a power switch (Fig. 2; VFB and BG1 have a common node) of each of the plurality of voltage converters and an error voltage between the output voltage and a first reference voltage (paragraph 0025; “a feedback signal that represents an output voltage of the multi-phase interleaved converter”) and an interleaving controller (Fig. 2; reference signal generator), coupled between the feedback circuit and the plurality of voltage converters, wherein the interleaving controller comprises a plurality of phase-locked loops (paragraph 0012; “a phase-locked loop (PLL) may be used to obtain the phase difference.”) respectively corresponding to the plurality of voltage converters, the interleaving controller turns on or off a phase-locking mechanism according to a zero-crossing detection state of the power switch (paragraph 0024; “In one interleaved control approach, an on time control circuit can be utilized to realize interleaved control through a PLL. For example, the PLL circuit can receive a clock signal, and may output an off signal.” and Fig. 2; Isense1,2,3 from power switch current sensor), and generates the plurality of control signals (Fig. 2; Ref 1,2,3) according to the plurality of feedback signals and the zero-crossing detection state (Fig. 4; reference signal generator includes Isense and FB) respectively.
-Regarding claim 2:
Hang discloses:
The voltage conversion circuit according to claim 1, wherein the plurality of voltage converters (Fig. 2; CH1,2,3)comprise: a first voltage converter (Fig. 2; CH1), receiving an input voltage (Fig. 2; VIN); and a second voltage converter, wherein an output terminal of the second voltage converter is coupled to an output terminal of the first voltage converter (Fig. 2; a first voltage converter and a second voltage converter have a common node into VOUT), and the second voltage converter receives the input voltage (Fig. 2; VIN), wherein the first voltage converter and the second voltage converter convert the input voltage according to a first control signal and a second control signal respectively to jointly generate the output voltage (Fig. 2; PWM for each voltage converter generates the output voltage).
-Regarding claim 3:
Hang discloses:
The voltage conversion circuit according to claim 2, further comprising: a first current sensor (Fig. 2; ISENSE), configured to sense a current on a first power switch (Fig. 2; circle near BG1 node, where a current on a first power switch is measured) of the first voltage converter to generate first current information, and to obtain a first zero-crossing detection state and first pattern information of the first power switch (Fig. 4; ISENSE into reference signal generator outputs Ref1 to get PWM1 through TOFF1) according to the first current information; and a second current sensor (Fig. 2; in CH2 even it is not described), configured to sense a current on a second power switch (Fig. 2; in CH2 even it is not described) of the second voltage converter to generate second current information (Fig. 2; in CH2 even it is not described), and to obtain a second zero-crossing detection state and second pattern information of the second power switch (Fig. 2; in CH2 even it is not described) according to the second current information.
Allowable Subject Matter
Claims 4-8, 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
The following is a statement of reasons for the indication of allowable subject matter:
-with respect to claim 4:
the prior art in Hang discloses the claimed invention in basic claim but do not further disclose about a feedback circuit very detail as in claim 4.
-with respect to claim 6:
the prior art in Hang discloses the claimed invention in basic claim but do not further disclose about the first signal treatment circuit and the second signal treatment circuit.
-with respect to claim 7:
the prior art in Hang discloses the claimed invention in basic claim but do not further disclose that the interleaving controller with a core circuit, PPL, pulse generator, and logic circuits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEUNG HO CHOI whose telephone number is (571)272-8188. The examiner can normally be reached Monday-Thursday, 7:30 AM - 5:30 PM ET.
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/SEUNG HO CHOI/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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