DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katsumata (US 2018/0248530).
In regard to Claim 1:
Katsumata discloses, in Figure 1, an amplifier comprising:
a signal input terminal configured to receive an input signal (RFin);
a signal output terminal configured to output an amplified signal (RFout);
an amplification circuit (10) coupled between the signal input terminal (RFin) and the signal output terminal (RFout), the amplification circuit (10) comprising a first transistor (FET1A), the first transistor comprising a first terminal (FET1A source), a second terminal (FET1A drain), a control terminal (FET1A gate) and a body terminal (FET1A body), wherein the first terminal of the first transistor (FET1A source) is coupled to a first node (gnd), the second terminal of first transistor (FET1A drain) is coupled to a second node (N1), the control terminal of first transistor (FET1A gate) is coupled to the signal input terminal (RFin), and the body terminal of first transistor is floating (¶ 0037); and
at least one variable voltage generation circuit (20) coupled to the amplification circuit (10); wherein:
during a transition period, the at least one variable voltage generation circuit (20) provides a first voltage difference between the second terminal and the first terminal of the first transistor (FET1A, ¶ 0055); and
during a steady period, the at least one variable voltage generation circuit (20) provides a second voltage difference between the second terminal and the first terminal of the first transistor (FET1A, ¶ 0058); and
the first voltage difference is greater than the second voltage difference (¶ 0059).
In regard to Claim 2:
Katsumata discloses, in Figure 1, the amplifier of claim 1, wherein:
the amplification circuit (10) further comprises: a second transistor (FET2A), comprising a first terminal (FET2A source), a second terminal (FET2A drain), and a control terminal (FET2A gate), wherein the first terminal of the second transistor (FET2A source) is coupled to the second node (N1), the second terminal of the second transistor (FET2A drain) is coupled to the signal output terminal (RFout), and the control terminal of the second transistor (FET2A gate) is coupled to a third node (VB2).
In regard to Claim 3:
Katsumata discloses, in Figure 1, the amplifier of claim 2, wherein:
the at least one variable voltage generation circuit comprises a first variable voltage generation circuit (20) coupled to the third node (VB2) and configured to provide a first pulse voltage signal at the third node (¶ 0021); during the transition period, the first pulse voltage signal has a first voltage level (¶ 0034); and during the steady period, the first pulse voltage signal has a second voltage level (¶ 0035).
In regard to Claim 5:
Katsumata discloses, in Figure 1, the amplifier of claim 3, wherein the first voltage level is different from the second voltage level (¶ 0034-0035)
In regard to Claim 6:
Katsumata discloses, in Figure 1, the amplifier of claim 2, wherein the second transistor further comprises a body terminal, and the body terminal of the second transistor is floating or contacted (¶ 0037).
In regard to Claim 16:
Katsumata discloses, in Figure 1, the amplifier of claim 1, wherein: during the transition period, a current flowing through the first transistor is substantially unstable (¶ 0047); and during the steady period, the current flowing through the first transistor is substantially stable (¶ 0047).
In regard to Claim 17:
Katsumata discloses, in Figure 1, an operation method for an amplifier, wherein:
the amplifier comprises:
a signal input terminal configured to receive an input signal (RFin);
a signal output terminal configured to output an amplified signal (RFout);
an amplification circuit (10) coupled between the signal input terminal (RFin) and the signal output terminal (RFout), the amplification circuit (10) comprising a first transistor (FET1A), the first transistor comprising a first terminal (FET1A source), a second terminal (FET1A drain), a control terminal (FET1A gate) and a body terminal (FET1A body), wherein the first terminal of the first transistor (FET1A source) is coupled to a first node (gnd), the second terminal of first transistor (FET1A drain) is coupled to a second node (N1), the control terminal of first transistor (FET1A gate) is coupled to the signal input terminal (RFin), and the body terminal of first transistor is floating (¶ 0037); and at least one variable voltage generation circuit (20) coupled to the amplification circuit (10); and
the operation method comprises:
during a transition period, the at least one variable voltage generation circuit (20) provides a first voltage difference between the second terminal and the first terminal of the first transistor (FET1A, ¶ 0055); and
during a steady period, the at least one variable voltage generation circuit (20) provides a second voltage difference between the second terminal and the first terminal of the first transistor (FET1A, ¶ 0058); and
the first voltage difference is greater than the second voltage difference (¶ 0059).
In regard to Claim 18:
Katsumata discloses, in Figure 1, The operation method of claim 17, wherein:
the amplification circuit further comprises:
a second transistor (FET2A), comprising a first terminal (FET2A source), a second terminal (FET2A drain), and a control terminal (FET2A gate), wherein the first terminal of the second transistor (FET2A source) is coupled to the second node (N1), the second terminal of the second transistor (FET2A drain) is coupled to the signal output terminal (RFout), and the control terminal of the second transistor (FET2A gate) is coupled to a third node (VB2);
the at least one variable voltage generation circuit comprises a first variable voltage generation circuit (20) coupled to the third node (VB2); and the method further comprises:
the first variable voltage generation circuit (20) providing a first pulse voltage signal at the third node (¶ 0021);
wherein:
during the transition period, the first pulse voltage signal has a first voltage level (¶ 0034); and
during the steady period, the first pulse voltage signal has a second voltage level (¶ 0035).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Katsumata (US 2018/0248530).
In regard to Claim 15:
Katsumata discloses the claimed invention except for wherein a duration of the transition period is substantially between 360 nanoseconds and 440 nanoseconds. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a duration of the transition period be substantially between 360 nanoseconds and 440 nanoseconds, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 4, 7-14, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 4:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein: during the transition period, a voltage level at the second terminal of the first transistor is determined by the first voltage level of the first pulse voltage signal; during the steady period, the voltage level at the second terminal of the first transistor is determined by the second voltage level of the first pulse voltage signal; and during both the transition period and the steady period, a voltage level at the first terminal of the first transistor remains substantially unchanged.
In regard to Claim 7:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein: the second terminal of the second transistor is further coupled to an operation voltage terminal; during the transition period, the operation voltage terminal provides a first operation voltage; during the steady period, the operation voltage terminal provides a second operation voltage; and the first operation voltage is higher than the second operation voltage.
In regard to Claim 8:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein: the at least one variable voltage generation circuit comprises a second variable voltage generation circuit coupled to the second node and configured to provide a second pulse voltage signal at the second node; during the transition period, the second pulse voltage signal has a third voltage level; and during the steady period, the second pulse voltage signal has a fourth voltage level.
In regard to Claim 11:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein: the at least one variable voltage generation circuit comprises a third variable voltage generation circuit coupled to the first node and configured to provide a third pulse voltage signal at the first node; during the transition period, the third pulse voltage signal has a fifth voltage level; and during the steady period, the third pulse voltage signal has a sixth voltage level.
In regard to Claim 19:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein: the at least one variable voltage generation circuit comprises a second variable voltage generation circuit coupled to the second node; and the method further comprises: the second variable voltage generation circuit providing a second pulse voltage signal at the second node; wherein: during the transition period, the second pulse voltage signal has a third voltage level; and during the steady period, the second pulse voltage signal has a fourth voltage level.
In regard to Claim 20:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein: the at least one variable voltage generation circuit comprises a third variable voltage generation circuit coupled to the first node; and the method further comprises: the third variable voltage generation circuit providing a third pulse voltage signal at the first node; wherein: during the transition period, the third pulse voltage signal has a fifth voltage level; and during the steady period, the third pulse voltage signal has a sixth voltage level.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US 2018/01991308) discloses an amplifier device includes an amplifying unit, a bias module and an impedance unit. A first end of the amplifying unit electronically connects to a voltage source. A second end of the amplifying unit receives an input signal. The first end of the amplifying unit outputs an output signal amplified by the amplifying unit. A third end of the amplifying unit connects to a first reference potential. The bias module electrically connects to the second end of the amplifying unit for providing a bias voltage to the amplifying unit. An impedance unit is electrically connects to the bias module. An impedance value of the impedance unit is variable.
Seshita et al. (US 2018/0062581) discloses a high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.
Chen et al. (US 2019/0267949) discloses an amplifier device includes an amplifying unit, a bias module, an impedance unit and an adjusting module. The amplifying unit has a first end coupled to a voltage source and used for outputting an output signal amplified by the amplifying unit, a second end used for receiving an input signal, and a third end coupled to a first reference potential terminal. The bias module is coupled to the second end of the amplifying unit, and provides a bias voltage to the amplifying unit and adjusts linearity of the amplifier device according to a source voltage from the voltage source.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
