DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 3 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention. There is no indication from the specification that the dimensions of the plurality of first spacers are not completely the same.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-8, 10-13, 15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2013/0342782).
As to claim 1, Kim discloses in figures 1-3: an array substrate 100 including a first substrate 110, a plurality of sub-pixels disposed on the first substrate and arranged in an array and a plurality of gate lines 121a/121b disposed on the first substrate, wherein one or more gate lines of the plurality of gate lines are located between two adjacent rows of sub-pixels; and an opposite substrate 200 arranged opposite to the array substrate, and including a second substrate 210 and a plurality of first spacers SS3 disposed on a side of the second substrate proximate to the array substrate; wherein an orthographic projection of a first spacer on the array substrate is located in a region where a region between the two adjacent rows of sub-pixels intersects with a region between two adjacent columns of sub-pixels, and an orthographic projection of the first spacer on the first substrate overlaps with an orthographic projection of at least one gate line of the one or more gate lines on the first substrate; the array substrate further includes a thin film transistor Q (see figure 1) disposed in a sub-pixel, wherein thin film transistors in two adjacent sub-pixels in a row of sub-pixels are respectively located on two opposite sides of the row of sub-pixels in a column direction in which the plurality of sub-pixels are arranged; and for the two opposite sides of the row of sub-pixels in the column direction, a thin film transistor of the thin film transistors in the two adjacent sub-pixels on a side is coupled to a gate line disposed on a same side as the thin film transistor on the side, and another thin film transistor of the thin film transistors in the two adjacent sub-pixels on another side is coupled to a gate line disposed on a same side as the thin film transistor on the another side.
As to claim 2, Kim discloses all of the elements of the claimed invention discussed above regarding claim 1. Kim further discloses in figure 2, wherein two gate lines 121a and 121b are located between the two adjacent rows of sub-pixels, and the orthographic projection of the first spacer SS3 on the first substrate overlaps with both orthographic projections of the two gate lines on the first substrate (see also figure 7).
As to claim 4, Kim discloses all of the elements of the claimed invention discussed above regarding claim 1. Kim further discloses in figure 2, wherein the orthographic projection of the first spacer SS3 on the first substrate is non-overlapping with an orthographic projection of the thin film transistor on the first substrate.
As to claim 5, Kim discloses all of the elements of the claimed invention discussed above regarding claim 1. Kim further discloses in figure 2, wherein the opposite substrate further includes a plurality of second spacers MS1/SS1/SS2; wherein orthographic projections of the plurality of second spacers on the second substrate are non-overlapping with orthographic projections of the plurality of first spacers on the second substrate; and the plurality of second spacers are arranged in a plurality of columns, second spacers in each column are arranged in the column direction in which the plurality of sub-pixels are arranged, orthographic projections of the second spacers in each column on the array substrate are located in a column region where a column of sub-pixels are located.
As to claim 6, Kim discloses all of the elements of the claimed invention discussed above regarding claim 5. Kim further discloses in figure 2, wherein an orthographic projection of a second spacer MS1 on the first substrate overlaps with an orthographic projection of the thin film transistor on the first substrate.
As to claim 7, Kim discloses all of the elements of the claimed invention discussed above regarding claim 5. Kim further discloses in figure 2, wherein the orthographic projection of the second spacer SS1/SS2 on the first substrate overlaps with an orthographic projection of at least one gate line of the one or more gate lines on the first substrate.
As to claim 8, Kim discloses all of the elements of the claimed invention discussed above regarding claim 7. Kim further discloses in figure 2, wherein in the column direction in which the plurality of sub-pixels are arranged, a gate line of the at least one gate line has a protruding portion (gate lines protrude to form gate electrodes); and an orthographic projection of the second spacer MS1 on the array substrate is located in a region where the protruding portion of the gate line is located.
As to claim 10, Kim discloses all of the elements of the claimed invention discussed above regarding claim 7. Kim further discloses in figure 2, wherein two gate lines 121a/121b are located between the two adjacent rows of sub-pixels, and the orthographic projection of the second spacer SS1/SS2 on the first substrate overlaps with both orthographic projections of the two gate lines on the first substrate (see also figures 5-6).
As to claim 11, Kim discloses all of the elements of the claimed invention discussed above regarding claim 7. Kim further discloses in figure 2, wherein two gate lines 121a/121b are located between the two adjacent rows of sub-pixels, wherein in the region between the two adjacent rows of sub-pixels, an orthographic projection of a second spacer SS1 in two adjacent second spacers on the first substrate overlaps with an orthographic projection of a gate line 121a in the two gate lines on the first substrate, and an orthographic projection of another second spacer SS2 in the two adjacent second spacers on the first substrate overlaps with an orthographic projection of another gate line 121b in the two gate lines on the first substrate.
As to claim 12, Kim discloses all of the elements of the claimed invention discussed above regarding claim 5. Kim further discloses wherein the plurality of second spacers and the plurality of first spacers are disposed in a same layer.
As to claim 13, Kim discloses all of the elements of the claimed invention discussed above regarding claim 5. Kim further discloses in figures 5-7, wherein a dimension of the first spacer SS1 and a dimension of the second spacer SS2/SS3 in a direction perpendicular to a plane where the second substrate is located are approximately equal.
As to claim 15, Kim discloses all of the elements of the claimed invention discussed above regarding claim 1. Kim further discloses in figure 2, wherein the array substrate further includes a plurality of data lines 171 disposed on the first substrate, wherein two adjacent columns of sub-pixels are coupled to a data line.
As to claim 17, Kim discloses all of the elements of the claimed invention discussed above regarding claim 1. Kim further discloses in figure 3, wherein the array substrate further includes a plurality of first electrodes 191 disposed on the first substrate, a first electrode is located in the sub-pixel, and the first electrode is coupled to the thin film transistor; and the opposite substrate further includes a second electrode disposed 270 on the second substrate, the second electrode is located on a side of the first spacers proximate to the second substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2013/0342782).
As to claim 14, Kim discloses all of the elements of the claimed invention discussed above regarding claim 5, but does not disclose wherein in a unit area of 1 mm² of the array substrate, a sum of an area of a surface of the first spacer away from the second substrate and an area of a surface of the second spacer away from the second substrate is greater than 10000 µm2. However, this parameter essentially describes the size and density of the first and second spacers, which was a matter of design choice based on the desired level of support for the cell gap. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim wherein in a unit area of 1 mm2 of the array substrate, a sum of an area of a surface of the first spacer away from the second substrate and an area of a surface of the second spacer away from the second substrate is greater than 10000 µm2 in order to provide appropriate support for the cell gap.
As to claim 18, Kim discloses all of the elements of the claimed invention discussed above regarding claim 1, but does not disclose wherein the array substrate further includes a first electrode and a second electrode disposed on the first substrate and located in the sub-pixel; the first electrode is a planar electrode, and the second electrode is a slit electrode, the first electrode is closer to the first substrate than the second electrode; and one of the first electrode and the second electrode is coupled to the thin film transistor. However, the recited structure describes a fringe field switching (FFS) liquid crystal display device, which was well known for its high image quality. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim wherein the array substrate further includes a first electrode and a second electrode disposed on the first substrate and located in the sub-pixel; the first electrode is a planar electrode, and the second electrode is a slit electrode, the first electrode is closer to the first substrate than the second electrode; and one of the first electrode and the second electrode is coupled to the thin film transistor, in order to obtain high image quality by forming a fringe field switching (FFS) liquid crystal display device.
Allowable Subject Matter
Claims 9, 16 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/DAVID Y CHUNG/Primary Examiner, Art Unit 2871
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