DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 11/20/2024 are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 9-10, 12-14, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fry et al (US 20110029807 A1), hereinafter referred as Fry, in view of Healy et al (US 20160239663 A1), hereinafter referred as Healy.
As per claim 1, Fry substantially teaches a method comprising:
receiving first data from a first portion of a memory device array (A read to a memory scrub address is completed as indicated in a block 500. An EDC check, often referred to as ECC check, performed by a memory controller, such as memory controller 108 of FIG. 1, memory controller 202 of FIG. 2, or memory controller 302 of FIG. 3, is completed on the received data and check bits from the read as indicated in a block; Fry p. 0042);
determining a quantity of correctable errors in the first data (If the data is not correctable, an uncorrectable error (UE) error recovery routine is initiated as indicated at a block…when the data is correctable, checking is performed to determine whether a register is set to log correctable errors (CEs), such as a register in a memory controller, for example, a register in memory controller 108 of FIG. 1, memory controller 202 of FIG. 2, or memory controller 302 of FIG. 3, as indicated in a decision block 610. If the register is set, the CE counter is incremented as indicated in a block 612. If the register is not set, then operations continue without incrementing the counter as indicated in a block; Fry p. 0052-0053);
Fry partially teaches the threshold comparison concept (a bus calibration is implemented responsive to a predefined intermittent error count. When the bus calibration fails or a predetermined number of intermittent errors occur over a predetermined period of time, a bus fault error recovery mode is initiated; Fry p. 0009) but does not express the claimed quantity of correctable errors in the first data.
Fry also partially teaches based on the relationship, one of performing a data scrub operation using the first data and the first portion of the memory array (scrub for intermittent fails may optionally replace the normal or conventional scrub such as illustrated in FIG. 5--e.g. in response to an increase in intermittent read errors; Fry p. 0051). The scrub is performed in response to an increase intermittent read errors not an explicit threshold comparison.
However, Healy in an analogous art teaches determining a relationship between the determined quantity of correctable errors and a specified threshold quantity of correctable errors (the ECC controller may compare the error count to an error threshold. The error threshold may be, e.g., the maximum number of errors tolerable in the DRAM. If the error count ("quantity") is below the threshold, the method ends…ECC controller determines that the error count exceeds the error threshold, the ECC controller will set an error flag, as depicted in operation…he memory controller may compare the total number of new errors to a threshold; Healy p. 0038-0040) and, based on the relationship, one of performing a data scrub operation using the first data and the first portion of the memory array (A “repair action” ("data scrub operation") includes any action performed on the DRAM (dynamic random access memory) to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation; Healy p. 0022) (the memory controller may schedule a repair action per operation 310. In some embodiments, the memory controller may immediately perform the repair action after determining that there is a significant number of new errors and available repair resources; Healy p. 0042) or inhibiting a data scrub operation using the first data and the first portion of the memory array (If the error count is below the threshold, the method ends (end equates inhibiting); Healy p. 0038).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Fry with the teachings of Healy by determining a relationship between the determined quantity of correctable errors and a specified threshold quantity and then performing a data scrub operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ performing an scrub operation based on the comparison of a quantity of correctable errors (CE) and a specified threshold in the system of Fry because Healy teaches comparing the error count to an error threshold to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring (Healy p. 0021).
As per claim 2, Fry in view of Healy teaches the method of claim 1,
wherein determining the quantity of correctable errors in the first data includes using a Reed-Solomon error-correcting code (The ECC controller 108 may be configured to perform forward error correction (FEC) on the DRAM 106 using the check bits 107 and an error-correcting code, such as a Hamming Code or a Reed-Solomon Code; Healy p. 0027).
As per claim 4, Fry in view of Healy teaches the method of claim 1,
wherein performing or inhibiting the data scrub operation includes performing the data scrub operation (using memory scrub operations to determine a frequency of intermittent correctable errors in accordance with the preferred embodiment; Fry p. 0024) (A “repair action” (type of “data scrub operation") includes any action performed on the DRAM (dynamic random access memory) to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation; Healy p. 0022) when the determined quantity of correctable errors is less than the specified threshold quantity of correctable errors (the ECC controller may compare the error count to an error threshold. The error threshold may be, e.g., the maximum number of errors tolerable in the DRAM. If the error count ("quantity") is below the threshold, the method ends…ECC controller determines that the error count exceeds the error threshold, the ECC controller will set an error flag, as depicted in operation…he memory controller may compare the total number of new errors to a threshold; Healy p. 0038-0040), and inhibiting the data scrub operation when the determined quantity of correctable errors meets or exceeds the specified threshold quantity of correctable errors (If the error count exceeds its associated threshold, the failure detection unit may alert the memory controller 105 at operation 512, and the process may end ("inhibiting operation"); Healy p. 0053).
As per claim 9, Fry in view of Healy teaches the method of claim 1, further comprising:
performing the data scrub operation using the first data from the first portion of the memory array (A read to a memory scrub address is completed as indicated in a block 500. An EDC check, often referred to as ECC check, performed by a memory controller, such as memory controller 108 of FIG. 1, memory controller 202 of FIG. 2, or memory controller 302 of FIG. 3, is completed on the received data and check bits from the read as indicated in a block; Fry p. 0042);
receiving second data from the same first portion of the memory device array; determining a second quantity of correctable errors in the second data (Inherent in Fry's periodic scrub process (Fry p. 0012)) (If the data is not correctable, an uncorrectable error (UE) error recovery routine is initiated as indicated at a block…when the data is correctable, checking is performed to determine whether a register is set to log correctable errors (CEs), such as a register in a memory controller, for example, a register in memory controller 108 of FIG. 1, memory controller 202 of FIG. 2, or memory controller 302 of FIG. 3, as indicated in a decision block 610. If the register is set, the CE counter is incremented as indicated in a block 612. If the register is not set, then operations continue without incrementing the counter as indicated in a block; Fry p. 0052-0053);
and responsive to the second quantity of correctable errors in the second data meeting the specified threshold quantity of correctable errors, inhibiting a second data scrub operation (the ECC controller may compare the error count to an error threshold. The error threshold may be, e.g., the maximum number of errors tolerable in the DRAM. If the error count ("quantity") is below the threshold, the method ends…ECC controller determines that the error count exceeds the error threshold, the ECC controller will set an error flag, as depicted in operation…he memory controller may compare the total number of new errors to a threshold; Healy p. 0038-0040)(If the error count exceeds its associated threshold, the failure detection unit may alert the memory controller 105 at operation 512, and the process may end ("inhibiting operation"); Healy p. 0053).
As per claim 10, Fry in view of Healy teaches the method of claim 9, further comprising notifying a host device that the first portion of the memory array contains an uncorrectable error (the error logging unit 110 may store bank-specific error counts that tally the number of errors found in particular memory banks within the DRAM 106. Additionally, the error logging unit 110 may store an uncorrectable error flag that alerts the memory controller 105 whenever an uncorrectable error is found in the DRAM 106… upon detecting an error, the ECC controller 108 may alert the memory controller 105 to the location of the error; Healy p. 0029).
As per claim 12, Fry substantially teaches A system comprising:
a host device (Computer system 100 includes one or more processors; Fry p. 0024);
and a memory device coupled to the host device, wherein the memory device comprises a memory device controller configured to (Computer system 100 includes a memory system 106 including a memory controller 108 including an error log and one or more counters 109 in accordance with an embodiment of the invention and a main memory 110 connected by a bus; Fry p. 0025):
monitor correctable error accumulation in each of multiple regions of a memory array (A number of intermittent errors is tracked, where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads; Fry p. 0008, 0022);
Fry does not teach conditionally trigger a scrub operation.
However Healy in an analogous art teaches conditionally trigger a scrub operation (A “repair action” ("data scrub operation") includes any action performed on the DRAM (dynamic random access memory) to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation; Healy p. 0022) based on a number of correctable errors observed (The error count is a running tally of the number of errors discovered by the ECC controller. The ECC controller 108 may be further configured to increment the ECR 110B when it detects a soft error, and to save information about the error, such as the row and column address of an error, in the EAR bank 110A; Healy p. 0026-0027).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Fry with the teachings of Healy by determining a relationship between the determined quantity of correctable errors and a specified threshold quantity and then performing a data scrub operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ performing an scrub operation based on the comparison of a quantity of correctable errors (CE) and a specified threshold in the system of Fry because Healy teaches comparing the error count to an error threshold to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring (Healy p. 0021).
As per claim 13, Fry in view of Healy teaches the system of claim 12,
wherein the memory device controller is configured to perform the scrub operation (A “repair action” ("data scrub operation") includes any action performed on the DRAM (dynamic random access memory) to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation; Healy p. 0022) for particular data read from a first region of the memory array (performs at least two reads before moving to a next memory scrub address; Fry p. 0022) when the error accumulation associated with the first region of the memory array (a memory controller 108 including an error log and one or more counters 109 in accordance with an embodiment of the invention and a main memory 110 connected by a bus; Fry p. 0025) (The method of the invention tracks a number of intermittent errors, where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads; Fry p. 0022) indicates less than a threshold number of correctable errors (An “error indicator” is any information about the DRAM that may be compared to established thresholds to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring. For example, an error indicator may be the error count, the error rate, the error acceleration, or the DRAM temperature. An “associated threshold” is a threshold that corresponds to a given error indicator. For example, the associated threshold of an error count may be the maximum number of errors the DRAM can tolerate, while the associated threshold of an error rate may be the maximum tolerable rate of new errors in the DRAM; Healy p. 0021) (If the error count is below the threshold, the method ends; Healy p. 0038).
As per claim 14, Fry in view of Healy teaches the system of claim 13,
wherein the memory device controller is configured to not perform the scrub operation for the particular data (A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM (once the error condition warrants it, the controller performs a different repair action instead of continuing normal operation); Healy p. 0022) when the error accumulation associated with the first region of the memory array (a memory controller 108 including an error log and one or more counters 109 in accordance with an embodiment of the invention and a main memory 110 connected by a bus; Fry p. 0025) (The method of the invention tracks a number of intermittent errors, where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads; Fry p. 0022) indicates at least the threshold number of correctable errors (An “error indicator” is any information about the DRAM that may be compared to established thresholds to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring. For example, an error indicator may be the error count, the error rate, the error acceleration, or the DRAM temperature. An “associated threshold” is a threshold that corresponds to a given error indicator. For example, the associated threshold of an error count may be the maximum number of errors the DRAM can tolerate, while the associated threshold of an error rate may be the maximum tolerable rate of new errors in the DRAM; Healy p. 0021) (If the error count is below the threshold, the method ends; Healy p. 0038).
As per claim 17, Fry in view of Healy teaches the system of claim 13,
wherein the memory device controller is configured to monitor the correctable error accumulation for the same regions of the memory array over multiple scrub operation cycles (performs at least two reads before moving to a next memory scrub address. The method of the invention tracks a number of intermittent errors, where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads; Fry p. 0022) and, in response to identify the same correctable errors in the same regions of the memory array over multiple scrub operation cycles, the memory device controller is configured to notify the host device (the error logging unit 110 may store an uncorrectable error flag that alerts the memory controller 105 whenever an uncorrectable error is found in the DRAM 106…the ECC controller 108 may alert the memory controller 105 to the location of the error; Healy p. 0028-0029) that the memory array includes one or more regions for repair or remapping (A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM (once the error condition warrants it, the controller performs a different repair action instead of continuing normal operation); Healy p. 0022).
As per claim 19, Fry teaches a non-transitory processor-readable storage medium, the processor-readable storage medium including instructions that, when executed by a processor circuit, cause the processor circuit to (Main memory is typically coupled to a processor (Fry p. 0004) Main memory 110 is comprised of, for example, a dynamic random access memory (DRAM), a synchronous direct random access memory (SDRAM), a current double data rate (DDRX) SDRAM, non-volatile memory, optical storage, and other storage devices (p. Fry p. 0025)):
read first data from a first portion of an array of a memory device (A memory scrub for intermittent fails performs at least two reads before moving to a next memory scrub address; Fry p. 0008) (The novel memory scrub operation of the invention is called a scrub for intermittent fails; Fry p. 0022);
the scrub operation including determining corrected data based on the first data ("Correct data using EDC syndrome bits; Fry Fig. 5) and writing the corrected data to the first portion of the array of the memory device (when the first read and the second read fail, a modify write is performed at the failing memory address before moving to a next memory scrub address; Fry p. 0010);
Fry does not explicitly teach use an error-correcting code decoder to determine a number of correctable errors present in the first data;
in response to the number of correctable errors being less than a specified threshold number of correctable errors, perform a scrub operation using the first data;
and in response to the number of correctable errors being greater than or equal to a specified threshold number of correctable errors, disallow the scrub operation
However, Healy in an analogous art teaches use an error-correcting code decoder to determine a number of correctable errors present in the first data (The ECR 110B may be a register in which an error count is stored. The error count is a running tally of the number of errors discovered by the ECC controller 108. Both the ECR 110B and the EAR bank 110A may be reset periodically…The ECC controller 108 may be configured to perform forward error correction (FEC) on the DRAM 106 using the check bits 107 and an error-correcting code, such as a Hamming Code or a Reed-Solomon Code. The number of check bits 107 stored on the memory may depend on both the size of the DRAM 106 and the error-correcting code used. The ECC controller 108 may be further configured to increment the ECR 110B when it detects a soft error, and to save information about the error, such as the row and column address of an error, in the EAR bank 110; Healy p. 0026-0027);
in response to the number of correctable errors being less than a specified threshold number of correctable errors, perform a scrub operation using the first data (An “error indicator” is any information about the DRAM that may be compared to established thresholds to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring. For example, an error indicator may be the error count, the error rate, the error acceleration, or the DRAM temperature. An “associated threshold” is a threshold that corresponds to a given error indicator. For example, the associated threshold of an error count may be the maximum number of errors the DRAM can tolerate, while the associated threshold of an error rate may be the maximum tolerable rate of new errors in the DRAM…A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation; Healy p. 0021-0022),
and in response to the number of correctable errors being greater than or equal to a specified threshold number of correctable errors, disallow the scrub operation (particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information (stopping operation) in the affected memory cell or row, or ultimately to replace the DRAM; Healy p. 0022)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Fry with the teachings of Healy by determining a relationship between the determined quantity of correctable errors and a specified threshold quantity and then performing a data scrub operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ performing an scrub operation based on the comparison of a quantity of correctable errors (CE) and a specified threshold in the system of Fry because Healy teaches comparing the error count to an error threshold to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring (Healy p. 0021).
Claims 3, 7-8, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Fry in view of Healy in further view of Chu et al (US 20180188954 A1), hereinafter referred as Chu.
As per claim 3, Fry in view of Healy teaches the method of claim 1. The combination of Fry and Healy does not teach wherein the first portion of the memory device array comprises a first die of multiple dies in the memory device array, and wherein determining the quantity of correctable errors in the first data includes determining the quantity of correctable errors in the first die.
However, Chu in an analogous art teaches wherein the first portion of the memory device array comprises
a first die of multiple dies in the memory device array (Data storage system 100 may include host system 110 and data storage device 120. Data storage device 120 (for example, a solid state drive) may include host interface 130, controller 140, memory 150, and non-volatile memory dies 160A-160n; Chu p. 0013) (The number of non-volatile memory dies 160A-160n in data storage device 120 may be any number such as two, four, eight, sixteen, etc. For simplicity of discussion, non-volatile memory dies 160A and 160B from non-volatile memory dies 160A-160n are depicted in FIG. 2. Non-volatile memory dies 160A and 160B are not limited to any particular capacity or configuration. Each of non-volatile memory dies 160A and 160B may be organized into blocks and pages; Chu p. 0022), and
wherein determining the quantity of correctable errors in the first data includes determining the quantity of correctable errors in the first die (Controller 140 sums error counts of the blocks for respective operation error types, and determines the total error counts of respective operation error types for each of non-volatile memory dies. For example, one error is marked for block 2A for read operation error type. Thus, controller 140 enters one in the column of total A for read operation error type in non-volatile memory die 160A. Controller repeats the same or similar steps to determine total error counts for all of operation error types in both non-volatile memory dies 160A and 160B; Chu p. 0032).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Fry in view of Healy with the teachings of Chu by configuring the first portion of the memory device array with a first die of multiple dies in the memory device array and determining the quantity of correctable errors in the first die.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ determining the quantity of correctable errors in a first die in the system of Fry in view of Healy because Chu teaches improving performance and reliability of data storage systems by monitoring data operation error counts of blocks across non-volatile memory die and excluding non-volatile memory die from future data operations when the data operation error counts for non-volatile memory die satisfy predetermined thresholds (Chu p. 0012).
As per claim 7, Fry in view of Healy teaches the method of claim 1. The combination of Fry, Healy and Chu teaches wherein the first portion of the memory device array comprises
multiple dies in the memory device array (Data storage system 100 may include host system 110 and data storage device 120. Data storage device 120 (for example, a solid state drive) may include host interface 130, controller 140, memory 150, and non-volatile memory dies 160A-160n; Chu p. 0013) (The number of non-volatile memory dies 160A-160n in data storage device 120 may be any number such as two, four, eight, sixteen, etc. For simplicity of discussion, non-volatile memory dies 160A and 160B from non-volatile memory dies 160A-160n are depicted in FIG. 2. Non-volatile memory dies 160A and 160B are not limited to any particular capacity or configuration. Each of non-volatile memory dies 160A and 160B may be organized into blocks and pages; Chu p. 0022), and
wherein determining the quantity of correctable errors in the first data includes determining respective quantities of correctable errors in each of the multiple dies (Controller 140 sums error counts of the blocks for respective operation error types, and determines the total error counts of respective operation error types for each of non-volatile memory dies. For example, one error is marked for block 2A for read operation error type. Thus, controller 140 enters one in the column of total A for read operation error type in non-volatile memory die 160A. Controller repeats the same or similar steps to determine total error counts for all of operation error types in both non-volatile memory dies 160A and 160B; Chu p. 0032).
As per claim 8, Fry in view of Healy in further view of Chu teaches the method of claim 7, further comprising
determining a distribution of correctable errors among the multiple dies (As stated in previous claim rejections, the combination of Fry and Healy teaches counting correctable errors (Fry). They do not explicitly teach distribution of correctable errors amongst the dies but once separate CE counts are available for each die, it would have been obvious to compare those counts to make more informed scrub decisions. However, Chu says “in each of non-volatile memory dies (i.e., non-volatile memory dies 160A and 160B) in data storage device 120, and one column indicating total error counts for respective data operation error types across a non-volatile memory die (separate totals for each die equates error distribution across dies” (Chu p. 0024) “Controller 140 sums error counts of the blocks for respective operation error types, and determines the total error counts of respective operation error types for each of non-volatile memory dies. For example, one error is marked for block 2A for read operation error type. Thus, controller 140 enters one in the column of total A for read operation error type in non-volatile memory die 160A. Controller repeats the same or similar steps to determine total error counts for all of operation error types in both non-volatile memory dies 160A and 160B” (Chu p. 0032), and performing or inhibiting the data scrub operation using the first data based on the determined distribution (Controller 140 may determine whether a total error count for a specific data operation error type for non-volatile memory die satisfies a predetermined threshold value after an error count for the specific data operation error type is incremented. Alternatively, controller 140 may perform the determination periodically or after a predetermined number of data operations are executed. Controller 140 may mark non-volatile memory die that includes one or more total error counts satisfying the predetermined threshold value for exclusion from future data operation; Chu p. 0034).
As per claim 15, Fry in view of Healy teaches the system of claim 13,
wherein the first region of the memory array comprises a first die (Data storage system 100 may include host system 110 and data storage device 120. Data storage device 120 (for example, a solid state drive) may include host interface 130, controller 140, memory 150, and non-volatile memory dies 160A-160n; Chu p. 0013) (The number of non-volatile memory dies 160A-160n in data storage device 120 may be any number such as two, four, eight, sixteen, etc. For simplicity of discussion, non-volatile memory dies 160A and 160B from non-volatile memory dies 160A-160n are depicted in FIG. 2. Non-volatile memory dies 160A and 160B are not limited to any particular capacity or configuration. Each of non-volatile memory dies 160A and 160B may be organized into blocks and pages; Chu p. 0022) of multiple dies in the memory array (in each of non-volatile memory dies (i.e., non-volatile memory dies 160A and 160B) in data storage device 120, and one column indicating total error counts for respective data operation error types across a non-volatile memory die (separate totals for each die equates error distribution across dies); Chu p. 0024).
Claims 5-6, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Fry in view of Healy in further view of LEE (US 20200226039 A1).
As per claim 5, Fry in view of Healy teaches the method of claim 1. The combination of Fry and Healy does not teach determining the first data includes a cluster of bit errors in the first data, wherein the cluster of bit errors corresponds to information from two or more adjacent cells, rows, or columns in a particular die of the memory device array.
However, LEE in an analogous art teaches determining the first data includes a cluster of bit errors in the first data (determining whether plural pieces of data (equates cluster of bit) outputted from memory cells corresponding to each column address in the target area are the same as each other; and determining whether an error is included in the plural pieces of data based on a type of data, a state of data and a column data comparison result between the plural pieces of data stored in the target area to cure the error; LEE p. 0043),
wherein the cluster of bit errors corresponds to information from two or more adjacent cells, rows, or columns (The volatile memory may include plural memory cells which are individually addressable through a row address corresponding to a word line and a column address corresponding to a bit line; LEE p. 0041) in a particular die of the memory device array (the memory device 150 may include plural memory dies coupled with the controller; LEE p. 0060).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Fry in view of Healy with the teachings of LEE by configuring a cluster of bit errors corresponding to information from two or more adjacent cells, row, or columns in a particular die.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ cluster of bit errors in a particular die in the system of Fry in view of Healy because LEE teaches plural memory cells, a column data checking circuitry to quickly and reliably process data into a memory device by reducing operational complexity and performance degradation of the memory system, thereby enhancing usage efficiency of the memory device (LEE p. 0024).
As per claim 6, Fry in view of Healy in further view of LEE teaches the method of claim 5, wherein performing or inhibiting the data scrub operation includes inhibiting the data scrub operation (If the error count exceeds its associated threshold, the failure detection unit may alert the memory controller 105 at operation 512, and the process may end ("inhibiting operation"); Healy p. 0053) when the first data includes the cluster of bit errors (determining whether plural pieces of data (equates cluster of bit) outputted from memory cells corresponding to each column address in the target area are the same as each other; and determining whether an error is included in the plural pieces of data based on a type of data, a state of data and a column data comparison result between the plural pieces of data stored in the target area to cure the error.; LEE p. 0043).
As per claim 16, Fry in view of Healy teaches the system of claim 13,
wherein the first region of the memory array comprises a first row (The volatile memory may include plural memory cells which are individually addressable through a row address corresponding to a word line and a column address corresponding to a bit line; LEE p. 0041) or a first column of memory cells in the memory array (corresponding to each column address in the target area are the same as each other; and determining whether an error is included in the plural pieces of data based on a type of data, a state of data and a column data comparison result between the plural pieces of data stored in the target area to cure the error; LEE p. 0043).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Fry in view of Healy in further view of Zimmer et al (US 20210311818 A1), hereinafter referred as Zimmer.
As per claim 11, Fry in view of Healy teaches the method of claim 1, further comprising:
performing the data scrub operation using the first data from the first portion of the memory array (A read to a memory scrub address is completed as indicated in a block 500. An EDC check, often referred to as ECC check, performed by a memory controller, such as memory controller 108 of FIG. 1, memory controller 202 of FIG. 2, or memory controller 302 of FIG. 3, is completed on the received data and check bits from the read as indicated in a block; Fry p. 0042);
receiving second data from the same first portion of the memory device array (Inherent in Fry's periodic scrub process (Fry p. 0012));
determining a second quantity of correctable errors in the second data (If the data is not correctable, an uncorrectable error (UE) error recovery routine is initiated as indicated at a block…when the data is correctable, checking is performed to determine whether a register is set to log correctable errors (CEs), such as a register in a memory controller, for example, a register in memory controller 108 of FIG. 1, memory controller 202 of FIG. 2, or memory controller 302 of FIG. 3, as indicated in a decision block 610. If the register is set, the CE counter is incremented as indicated in a block 612. If the register is not set, then operations continue without incrementing the counter as indicated in a block; Fry p. 0052-0053);
and responsive to the second quantity of correctable errors in the second data being less than the specified threshold quantity of correctable errors (the ECC controller may compare the error count to an error threshold. The error threshold may be, e.g., the maximum number of errors tolerable in the DRAM. If the error count ("quantity") is below the threshold, the method ends…ECC controller determines that the error count exceeds the error threshold, the ECC controller will set an error flag, as depicted in operation…he memory controller may compare the total number of new errors to a threshold; Healy p. 0038-0040).
Healy teaches "the repair action may be running a memory scrub operation. when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM" (Healy p. 0022) This teaches the concept of repairing or retiring a row but does not teach Post Package Repair (PPR)
However, Zimmer in an analogous art teaches determining whether a repair criteria is met for the first portion of the memory array (Illustrated processing block 612 determines whether a memory hardware failure has occurred (equates repair criterion as it is making a determination before deciding whether to invoke PPR); Zimmer p. 0040) and selectively performing a post package repair operation for the first portion of the memory array (correcting the memory error and bypassing the performance of the runtime post package repair in response to the determination that the computing system error is a memory error and the determination that the memory error is not a hardware failure…performance of the runtime post package repair may be performed in response to the determination that the computing system error is a memory error and the determination that the memory error is a hardware failure.; Zimmer p. 0041-0042).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Fry in view of Healy with the teachings of Zimmer by determining whether a repair criteria is met for the first portion of the memory array and performing a post package repair operation.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a post package repair operation in the system of Fry in view of Healy because Zimmer teaches runtime post package repair (PPR) procedures may advantageously operate without capacity loss, performance impact, and/or cost implication (Zimmer p. 0015).
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Fry in view of Healy in further view of Malladi et al (U.S. Patent Application No 202103116460 A1).
As per claim 18, Fry in view of Healy teaches the system of claim 13. The combination does not teach wherein the memory device is coupled to the host device using a compute express link (CXL) interconnect.
However, Malladi in an analogous art teaches wherein the memory device is coupled to the host device using a compute express link (CXL) interconnect (CXL may be capable of supporting cache coherence and CXL may be well suited for making connections to memory. CXL may further be used to provide connectivity between a host and accelerators, memory devices; Malladi p. 0041).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Fry in view of Healy with the teachings of Malladi by configuring the memory device to be coupled to the host device using a compute express link (CXL) interconnect.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ CXL interconnection in the system of Fry in view of Healy because Malladi teaches CXL coupling the host to the memory device to provide fixed, relatively short packet sizes, and, as a result, may be able to provide relatively high bandwidth and relatively low, fixed latency (Malladi p. 0041).
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fry in view of Healy in further view of Huang et al (US 20140026011 A1), hereinafter referred as Huang.
As per claim 20, Fry in view of Healy teaches the non-transitory processor-readable storage medium of claim 19,
wherein the processor-readable storage medium includes further instructions that, when executed by the processor circuit, cause the processor circuit to:
read second data from the first portion of the array of the memory device (Inherent in Fry's periodic scrub process (Fry p. 0012));
Fry in view of Healy does not teach determine whether the second data includes the same number of correctable errors present in the first data; and in response to determining the second data includes the same number of correctable errors, perform a repair operation on the first portion of the array of the memory device.
However, Huang in an analogous art teaches determine whether the second data includes the same number of correctable errors present in the first data (during read 32 a single bit error is detected. The ECC logic is capable of correcting that error and good data can be delivered to the host. In a following read 33, that same single bit error is detected. Sometime later, the next read 34 encounters a three bit error, which can include the original single bit error combined with two additional errors. The ECC logic may be able to correct the three bit error if it had been implemented with enough depth, or the limit of the ECC logic may have been exceeded. FIG. 3B shows a next read 35 which encounters the same three bit error; Huang p. 0027);
and in response to determining the second data includes the same number of correctable errors, perform a repair operation on the first portion of the array of the memory device (A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM (once the error condition warrants it, the controller performs a different repair action instead of continuing normal operation); Healy p. 0022)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Fry in view of Healy with the teachings of Huang by determining two sets of correctable error data to be the same.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ the same number of correctable errors to be present in two different sets of data in the system of Fry in view of Healy because Huang teaches to correct the error by merging the corrected bit with the data output from the array before it is applied to ECC logic in which the ECC is applied to the corresponding data to produce error checked data (Huang p. 0007)
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of References Cited).
The prior arts of record teach:
Hayek et al (US 5978952 A) teaches reading and rewriting each word within the indicated memory section--the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors
Carman et al (US 20130007541 A1) teaches an error module configured to perform a memory scrub of the memory across a scrub cycle of multiple scrub cycles. The error module is configured to identify correctable errors of symbols in the memory that are a result of accesses from a section of the memory in response to the memory scrub. The error module is configured to perform an analysis across the multiple scrub cycles, wherein the analysis comprises a determination whether at least two symbols across the multiple scrub cycles have at least one correctable error. The error module is configured to responsive to a determination that at least two symbols across the multiple scrub cycles have at least one correctable error, execute at least one repair of the memory that includes the section of memory.
Brewer et al (US 20220237077 A1) teaches a quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.
Conclusion
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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