DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are presented for examination.
Abstract
The abstract of the disclosure is acceptable for examination purposes.
Drawings
The drawings received on 11/20/2024 are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 6, 8-10, 15-16, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Malladi (U.S. Patent Application No 202103116460 A1), hereinafter referred as Malladi, in view of Norrie et al (U.S. Patent Application No 2024/0104045 A1), hereinafter referred as Norrie.
As per claim 1, Malladi teaches an apparatus, comprising:
a plurality of memory devices configured in a fabric (a fabric manager may be employed to (i) perform device discovery and virtual CXL software creation, and to (ii) bind virtual ports to physical ports. Such a fabric manager may operate through connections over an SMBus sideband. Each server can be populated with multiple direct-attached CXL attached memory modules; Malladi p.0045, 0049), comprising:
a first memory device configured to receive data from the single host device (it may (as mentioned above) virtualize the memory modules , i.e., operate as a translation layer, translating between processing circuit-side addresses (or “processor-side” addresses, i.e., addresses that are included in memory read and write commands issued by the processing circuits ) and memory-side addresses (i.e., addresses employed by the enhanced capability CXL switch to address storage locations in the memory modules ), thereby masking the physical addresses of the memory modules and presenting a virtual aggregation of memory; Malladi p. 0061);
and one or more second memory devices configured to receive the data from the first memory device via one or more peer-to-peer transfer operations (The controller of the enhanced capability CXL switch may facilitate a physical function (PF) to PF transfer (peer-to-peer). The processing circuit may send a CXL request, and data may be transmitted from one memory module to another memory module; p. 0066)
that are caused via a manager component for the fabric (The controller of the enhanced capability CXL switch may also act as a management device for the memory modules and help with host control plane processing; Malladi p. 0050),
the one or more peer-to-peer transfer operations to replicate the data from the first memory device to the one or more second memory devices (the data may be copied from one memory module to another memory module; Malladi p. 0066) without involvement of the single host device (The controller may transparently move data without the participation of the processing circuits and accordingly update the memory map (or “address translation table”) so that subsequent accesses function as expected; p. 0061) (the processing circuit may send a CXL request, and data may be transmitted from one memory module to another memory module behind the enhanced capability CXL switch without going to the processing circuit; Malladi p. 0066).
Malladi mentions connecting one root port to multiple end points (Malladi p. 0044) but does not explicitly teach a single host device.
However, Norrie in an analogous art teaches a single host device (Typically, a PCIe hierarchy is a tree that fans out of a single root port. This root port is commonly connected to a central processing unit (CPU) socket. Therefore, all devices on the PCIe hierarchy are available or accessible only to a single host server through this single root port (this equates to a single host device); Norrie p. 0003).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of MALLADI with the teachings of Norrie by configuring the apparatus to comprise a single host device .
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a single host device in the system of MALLADI because Norrie teaches ghost bridging allowing fine-grain sharing of device resources across multiple servers (p. 0021).
As per claim 4, Malladi in view of Norrie teaches the apparatus of claim 1. Malladi also teaches wherein the plurality of memory devices comprise a plurality of Compute Express Link (CXL) devices (The memory modules may be directly attached to the processing circuits as shown, and the top of rack Ethernet switch may be used for scaling the system to larger sizes (e.g., with larger numbers of servers); Malladi p. 0045, 0048-0049).
As per claim 6, Malladi in view of Norrie teaches the apparatus of claim 1. Malladi also teaches wherein the plurality of memory devices comprise a plurality of volatile or persistent memory devices (The system memory may include, e.g., DDR4 memory, DRAM, HBM, or LDPPR memory (volatile memory devices). The memory modules may be partitioned or contain cache controllers to handle multiple memory types; Malladi p. 0059, 0085) (one or more of the memory modules may include persistent memory, or “persistent storage” (i.e., storage within which data is not lost when external power is disconnected); Malladi p. 0051)
As per claim 8, Malladi in view of Norrie teaches the apparatus of claim 1. Malladi also teaches wherein the fabric comprises
one or more switches communicatively coupling the plurality of memory devices (Each input port of the enhanced capability CXL switch may independently access multiple output ports of the enhanced capability CXL switch and the memory modules connected thereto; Malladi p. 0045, 0049, 0060).
As per claim 9, Malladi in view of Norrie teaches the apparatus of claim 1. Malladi also teaches wherein the one or more peer-to-peer transfer operations are one or more Compute Express Link (CXL) memory operations (the controller of the enhanced capability CXL switch may facilitate a physical function (PF) to PF transfer. For example, if one of the processing circuits needs to move data from one physical address to another (which may have the same virtual addresses; this fact need not affect the operation of the processing circuit), or if the processing circuit needs to move data between two virtual addresses (which the processing circuit would need to have) the controller of the enhanced capability CXL switch may supervise the transfer, without the involvement of the processing circuit . For example, the processing circuit may send a CXL request, and data may be transmitted from one memory module to another memory module (e.g., the data may be copied from one memory module to another memory module) behind the enhanced capability CXL switch without going to the processing circuit; p. 0066)
As per claim 10, Malladi teaches a method, comprising:
loading data to a first memory device of a plurality of memory devices configured in a fabric (a fabric manager may be employed to (i) perform device discovery and virtual CXL software creation, and to (ii) bind virtual ports to physical ports. Such a fabric manager may operate through connections over an SMBus sideband. Each server can be populated with multiple direct-attached CXL attached memory modules; Malladi p.0045, 0049);
and causing, by the device, the first memory device to propagate the data to one or more second memory devices (it may (as mentioned above) virtualize the memory modules , i.e., operate as a translation layer, translating between processing circuit-side addresses (or “processor-side” addresses, i.e., addresses that are included in memory read and write commands issued by the processing circuits ) and memory-side addresses (i.e., addresses employed by the enhanced capability CXL switch to address storage locations in the memory modules ), thereby masking the physical addresses of the memory modules and presenting a virtual aggregation of memory; p. 0061), of the plurality of memory devices, via one or more peer-to-peer transfer operations (The controller of the enhanced capability CXL switch may facilitate a physical function (PF) to PF transfer (peer-to-peer). The processing circuit may send a CXL request, and data may be transmitted from one memory moduleto another memory module; p. 0066) to replicate the data from the first memory device to the one or more second memory devices (the data may be copied from one memory module to another memory module; p. 0066) without involvement of the single host device (The controller may transparently move data without the participation of the processing circuits and accordingly update the memory map (or “address translation table”) so that subsequent accesses function as expected; p. 0061) (the processing circuit may send a CXL request, and data may be transmitted from one memory module to another memory module behind the enhanced capability CXL switch without going to the processing circuit; p. 0066)
Malladi mentions connecting one root port to multiple end points (Malladi p. 0044) but does not explicitly teach a single host device.
However, Norrie in an analogous art teaches a single host device (Typically, a PCIe hierarchy is a tree that fans out of a single root port. This root port is commonly connected to a central processing unit (CPU) socket. Therefore, all devices on the PCIe hierarchy are available or accessible only to a single host server through this single root port (this equates to a single host device); Norrie p. 0003).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of MALLADI with the teachings of Norrie by configuring the apparatus to comprise a single host device .
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a single host device in the system of MALLADI because Norrie teaches ghost bridging allowing fine-grain sharing of device resources across multiple servers (p. 0021).
As per claim 15, Malladi teaches an apparatus, comprising:
a plurality of memory devices configured in a fabric with the single host device and a fabric manager, for the fabric, configured to (a fabric manager may be employed to (i) perform device discovery and virtual CXL software creation, and to (ii) bind virtual ports to physical ports. Such a fabric manager may operate through connections over an SMBus sideband. Each server can be populated with multiple direct-attached CXL attached memory modules; Malladi p.0045, 0049)
cause a first memory device, of the plurality of memory devices, to receive data from the single host device (it may (as mentioned above) virtualize the memory modules , i.e., operate as a translation layer, translating between processing circuit-side addresses (or “processor-side” addresses, i.e., addresses that are included in memory read and write commands issued by the processing circuits ) and memory-side addresses (i.e., addresses employed by the enhanced capability CXL switch to address storage locations in the memory modules ), thereby masking the physical addresses of the memory modules and presenting a virtual aggregation of memory; p. 0061);
and cause one or more second memory devices, of the plurality of memory devices, to receive the data from the first memory device via one or more peer-to-peer transfer operations (The controller of the enhanced capability CXL switch may facilitate a physical function (PF) to PF transfer (peer-to-peer). The processing circuit may send a CXL request, and data may be transmitted from one memory module to another memory module; p. 0066) without involvement of the single host device (The controller may transparently move data without the participation of the processing circuits and accordingly update the memory map (or “address translation table”) so that subsequent accesses function as expected; p. 0061) (the processing circuit may send a CXL request, and data may be transmitted from one memory module to another memory module behind the enhanced capability CXL switch without going to the processing circuit; p. 0066).
Malladi mentions connecting one root port to multiple end points (Malladi p. 0044) but does not explicitly teach a single host device.
However, Norrie in an analogous art teaches a single host device (Typically, a PCIe hierarchy is a tree that fans out of a single root port. This root port is commonly connected to a central processing unit (CPU) socket. Therefore, all devices on the PCIe hierarchy are available or accessible only to a single host server through this single root port (this equates to a single host device); Norrie p. 0003).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of MALLADI with the teachings of Norrie by configuring the apparatus to comprise a single host device .
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a single host device in the system of MALLADI because Norrie teaches ghost bridging allowing fine-grain sharing of device resources across multiple servers (p. 0021).
As per claim 16, Malladi in view of Norrie teaches the apparatus of claim 15, Malladi also teaches wherein the fabric manager is configured to cause the one or more second memory devices to receive the data from the first memory device via the one or more peer-to-peer transfers to replicate the data from the first memory device to the one or more second memory devices (the controller of the enhanced capability CXL switch may facilitate a physical function (PF) to PF transfer. For example, if one of the processing circuits needs to move data from one physical address to another (which may have the same virtual addresses; this fact need not affect the operation of the processing circuit), or if the processing circuit needs to move data between two virtual addresses (which the processing circuit would need to have) the controller of the enhanced capability CXL switch may supervise the transfer, without the involvement of the processing circuit . For example, the processing circuit may send a CXL request, and data may be transmitted from one memory module to another memory module (e.g., the data may be copied from one memory module to another memory module) behind the enhanced capability CXL switch without going to the processing circuit; Malladi p. 0066).
As per claim 19, Malladi in view of Norrie teaches the apparatus of claim 15, further comprising:
one or more switches communicatively coupling the plurality of memory devices (the system implements a aggregated architecture, including multiple servers, with each server aggregated with multiple CXL-attached memory modules . Each of the memory modules may contain multiple partitions that can separately be exposed as memory devices to multiple processing circuits . Each input port of the enhanced capability CXL switch may independently access multiple output ports of the enhanced capability CXL switch and the memory modules connected thereto; Malladi p. 0060)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi in view of Norrie in further view of Shin et al (U.S. Patent Application No 2011/0113296 A1), hereinafter referred as Shin.
As per claim 2, Malladi in view of Norrie teaches the apparatus of claim 1. Malladi also teaches wherein the one or more peer-to-peer transfer operations replicate the data from the first memory device to the one or more second memory devices (the processing circuit may send a CXL request, and data may be transmitted from one memory module to another memory module (e.g., the data may be copied from one memory module to another memory module) behind the enhanced capability CXL switch without going to the processing circuit; Malladi p. 0066) to enable testing of the first memory device and the one or more second memory devices.
Malladi fails to teach the enabling of testing of the first memory device and the one or more second memory devices.
However, Shin in an analogous art teaches the enabling of testing of the first memory device and the one or more second memory devices (The comparator may perform the testing operation in which the data may pass or fail, which may be determined by comparing the output data of the memory stored in a memory address with the expected data; p. 0080).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of Shin by configuring the peer-to-peer transfer operation to enable testing of the memory devices.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ testing of the memory devices in the system of Malladi in view of Norrie because Shin teaches transferring data to memory and comparing stored data with expected data is an effective technique for known testing methodology to enable validation of the memory device (Shin p. 0125).
Claims 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Malladi in view of Norrie in further view of Yudanov et al (U.S. Patent Application No 2021/0397932 A1), hereinafter referred as Yudanov.
As per claim 3, Malladi in view of Norrie teaches the apparatus of claim 1.
Malladi in view of Norrie fails to teach wherein the first memory device is further configured to perform processing in memory to modify the data that is to be replicated from the first memory device to the one or more second memory devices.
However, Yudanov in an analogous art teaches wherein the first memory device is further configured to perform processing in memory to modify the data that is to be replicated from the first memory device to the one or more second memory devices (a processing-in memory (PIM) capable device refers to a memory device capable of performing logical and arithmetic operations on data stored in an array of memory cells using a processing resource internal to the memory device; Malladi p. 0022, 0025, 0041-0042).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of Yudanov by configuring the memory device with processing-in memory (PIM).
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ PIM in the system of Malladi in view of Norrie because Yudanov teaches methods, apparatuses, and systems for in-or near-memory processing to save time and/or conserve power by reducing and possibly eliminating external communications (Yudanov p. 0020).
As per claim 17, Malladi in view of Norrie teaches the apparatus of claim 15.
Malladi in view of Norrie fails to teach wherein the fabric manager is configured to cause the one or more second memory devices to receive the data, as modified by the first memory device, via the one or more peer-to-peer transfers.
However, Yudanov in an analogous art teaches wherein the fabric manager is configured to cause the one or more second memory devices to receive the data, as modified by the first memory device, via the one or more peer-to-peer transfer (a processing-in memory (PIM) capable device refers to a memory device capable of performing logical and arithmetic operations on data stored in an array of memory cells using a processing resource internal to the memory device; Malladi p. 0022, 0025, 0041-0042).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of Yudanov by configuring the memory device with processing-in memory (PIM).
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ PIM in the system of Malladi in view of Norrie because Yudanov teaches methods, apparatuses, and systems for in-or near-memory processing to save time and/or conserve power by reducing and possibly eliminating external communications (Yudanov p. 0020).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi in view of Norrie in further view of TAKI (U.S Patent Application No 20220066636 A1).
As per claim 5, Malladi teaches the apparatus of claim 1.
Malladi in view of Norrie fails to teach wherein the plurality of memory devices comprise a plurality of accelerators.
However, TAKI in an analogous art teaches wherein the plurality of memory devices comprise a plurality of accelerators (The CXL device of Type 2 has an accelerator function to operate by coherently caching the host memory and/or the device memory. This accelerator function makes it possible to set whether the device memory as well as the host memory is coherently cached; TAKI p. 0031, 0034. 0036-0037)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of TAKI by configuring the memory devices to comprise accelerators.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ accelerators in the system of Malladi in view of Norrie because TAKI teaches a memory system connected to a host as a type 3 CXL device to support coherent caching involving host memory and/or the device memory with CXL architecture (TAKI p. 0034).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi in view of Norrie in further view of IKEDA (U.S Patent Application No 2008/0101104 A1).
As per claim 7, Malladi in view of Norrie teaches the apparatus of claim 1.
Malladi in view of Norrie fails to teach wherein the plurality of memory devices have a same configuration.
However, IKEDA in an analogous art teaches wherein the plurality of memory devices have a same configuration ((When all the stacked memory chips have same configuration, all the memory chips receive a common address. Therefore, all the memory chips are selected simultaneously. Although having same configuration, layers can be individually selected and activated with a layer address input externally by layer selection methods as described below, for example; IKEDA p. 0051).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of IKEDA by configuring the memory devices to have a same configuration.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ the same configuration amongst the memory devices in the system of Malladi in view of Norrie because IKEDA teaches when the stacked memory chips have same configuration, they can receive a common address simplifying addressing and control of the memory devices and having the size of a large-capacity semiconductor device is reduced (IKEDA p. 0005).
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Malladi in view of Norrie in further view of Abts et al (U.S. Patent Application No 2023/0161621 A1), hereinafter referred as Abts.
As per claim 11, Malladi in view of Norrie teaches the method of claim 10.
Malladi fails to teach wherein causing the first memory device to propagate the data to the one or more second memory devices comprises causing a fan-out propagation of the data.
However, Abts in an analogous art teaches wherein causing the first memory device to propagate the data to the one or more second memory devices comprises causing a fan-out propagation of the data (This “fan-out” and “fan-in” of the data allows for additional bandwidth (if available) to be utilized for transferring data to TSP2, allowing for the transfer of data to be completed in a more timely manner, despite the increase in path lengths of the individual routes; Abts p. 0080)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of Abts by configuring the memory device to cause a fan-out propagation of the data.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a fan-out propagation of the data in the system of Malladi in view of Norrie because Abts teaches fan-out communication for transferring data in a tensor steaming multiprocessor to use an otherwise under-utilized path with the goal of reducing latency and improving overall throughput (Abts p. 0082).
As per claim 14, Malladi in view of Norrie teaches the method of claim 10.
Malladi in view of Norrie fails to teach wherein the plurality of memory devices are communicatively coupled in a ring topology, a star topology, a mesh topology, or a tree topology.
However, Abts in an analogous art teaches wherein the plurality of memory devices are communicatively coupled in a ring topology, a star topology, a mesh topology, or a tree topology (high-level diagrams illustrating different types of network topologies, in accordance with some embodiments. Network system topologies can typically be classified as either indirect or direct networks; Abts FIG. 3A-3C; p. 0005, 0008, 0041).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of Abts by configuring the memory devices to be coupled in a specific topology.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ network topologies efficiency to the network diameter in the system of Malladi in view of Norrie because Abts teaches streaming multiprocessor for machine learning to reduce network latency (hop count) as well as lower the network cost to improve communication (Abts p. 0041).
Claims 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Malladi in view of Norrie in further view of Duncan et al (U.S. Patent Application No 2006/0123142), hereinafter referred as Duncan.
As per claim 12, Malladi in view of Norrie teaches the method of claim 10.
Malladi in view of Norrie fails to teach the method further comprising:
causing, by the device, the plurality of memory devices to return stored data to the single host device via one or more additional peer-to-peer transfer operations.
However, Duncan in an analogous art teaches causing, by the device, the plurality of memory devices to return stored data to the single host device via one or more additional peer-to-peer transfer operations (a second host logic for accessing a local memory within the second device to extract data identified by the read command, and a second fabric interface for returning the data from the second device to the first device through the interconnectivity fabric using the protocol; Duncan p. 0032; Claim 18).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of Duncan by configuring the device to cause the memory devices to return stored datat to the host.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ returning stored data to the host in the system of Malladi in view of Norrie because Duncan teaches returning stored data from the memory devices to the host in peer-to-peer communication over an interconnect fabric to provide processing speed and flexibility within the computing environment (Duncan p. 0005).
As per claim 18, Malladi in view of Norrie teaches the apparatus of claim 15.
Malladi in view of Norrie fails to teach wherein the fabric manager is further configured to cause the plurality of memory devices to return stored data to the single host device via one or more additional peer-to-peer transfer operations.
However, Duncan in an analogous art teaches wherein the fabric manager is further configured to cause the plurality of memory devices to return stored data to the single host device via one or more additional peer-to-peer transfer operations (a second host logic for accessing a local memory within the second device to extract data identified by the read command, and a second fabric interface for returning the data from the second device to the first device through the interconnectivity fabric using the protocol; Duncan p. 0032; Claim 18).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of Duncan by configuring the device to cause the memory devices to return stored datat to the host.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ returning stored data to the host in the system of Malladi in view of Norrie because Duncan teaches returning stored data from the memory devices to the host in peer-to-peer communication over an interconnect fabric to provide processing speed and flexibility within the computing environment (Duncan p. 0005).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi in view of Norrie in further view of Duncan and Abts.
As per claim 13, Malladi in view of Norrie in further view of Duncan teaches the method of claim 12.
Malladi in view of Norrie in further view of Duncan fails to teach causing the plurality of memory devices to return the stored data to the single host device comprises causing a fan-in returning of the stored data.
However, Abts in an analogous art teaches causing the plurality of memory devices to return the stored data to the single host device comprises causing a fan-in returning of the stored data (This “fan-out” and “fan-in” of the data allows for additional bandwidth (if available) to be utilized for transferring data to TSP2, allowing for the transfer of data to be completed in a more timely manner, despite the increase in path lengths of the individual routes; Abts p. 0080)
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie in further view of Duncan with the teachings of Abts by configuring the memory device to cause a fan-out propagation of the data.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a fan-out propagation of the data in the system of Malladi in view of Norrie in further view of Duncan because Abts teaches fan-out communication for transferring data in a tensor steaming multiprocessor to use an otherwise under-utilized path with the goal of reducing latency and improving overall throughput (Abts p. 0082).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi in view of Norrie in further view of Kwon et al (U.S. Patent Application No 2024/0378161 A1), hereinafter referred as Kwon.
As per claim 20, Malladi in view of Norrie teaches the apparatus of claim 19.
Malladi in view of Norrie fails to teach wherein the fabric manager is implemented in the one or more switches.
However, Kwon in an analogous art teaches wherein the fabric manager is implemented in the one or more switches (The at least one PBR switch may be configured to: identify types of neighboring ports connected to each port, collect information about the neighboring ports, and transmit the collected information to the fabric manager. The fabric manager may be configured to: determine a topology of the CXL network based on the collected information. The fabric manager may be configured to: assign PBR identifiers (IDs) for PBR flit routing to the upstream port and the downstream port of the PBR switch, respectively; and generate connectivity between PBR switches to determine the topology of the CXL network; Kwon p. 0008, 0011).
Therefore, it would have been obvious to one ordinary skill in the art, before the effective filing date of the invention, to modify the system of Malladi in view of Norrie with the teachings of Kwon by configuring the switched with a fabric manager.
This modification would have been obvious because one of ordinary skill in the art would have been motivated to employ a fabric manager in the switch in the system of Malladi in view of Norrie because Kwon teaches the fabric manager within the CXL switch to perform fabric and topology discovery and manage PBR switch (Kwon p. 0006-0008).
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. This information has been detailed in the PTO 892 attached (Notice of Reference Cited).
The prior arts of record teach:
KI et al (U.S. Patent Application No 20220113915 A1) teaches a memory system including one or more first type memory devices to receive first data, one or more second type memory devices to receive second data, and an accelerator configured to perform an operation using the first data and the second data. The memory system may further include a cache configured to cache the second data for the one or more second type memory devices. A device may include an interconnect interface, a memory system coupled to the interconnect interface to receive data, an accelerator coupled to the memory system, and virtualization logic configured to partition one or more resources of the accelerator into one or more virtual accelerators, wherein a first one of the one or more virtual accelerators may he configured to perform a first operation on a first portion of the data.
Archer et al (U.S. Patent Application No 20120179881 A1) teaches performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing, by that available core on the compute node, that next shared memory allreduce work unit.
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady, can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAYLUN A JACKSON/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
Prosecution Insights