DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because the empty boxes (e.g. 14,20, 22, 24; 32a-32c, 42a-42d; 102-114) in figures 1, 2, 3A, 3B and 4 should contain symbols or text indicating their functionality. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 11, 12 and 18 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Xu et al. (US 2019/0372063), hereinafter Xu.
Regarding claim 1, Xu discloses (see figures 1-6) a power inverter (figure 1A, part 106) comprising: a plurality of direct current (DC) bus bars (figures 2, 3, 5 and 6, parts 208a, 208b and 210) (paragraph [0027]; The DC busbars 208a, 208b and the AC busbar 210), wherein each of the plurality of DC bus bars (figures 2, 3, 5 and 6, parts 208a, 208b and 210) has a terminal end (figures 2, 3, 5 and 6, parts terminal end of 208a, 208b and 210) and a die attachment region (figures 2, 3, 5 and 6, parts die attachment region of 208a, 208b and 210); and a plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) (paragraph [0026]; The power module 202 may include a packaging structure 206 configured to receive a pair of switches 204, a pair of DC busbars 208, and an AC busbar 210… The switches 204 may be representative of a layout of the switches 110 described in reference to at least FIG. 1B. Each switch 204 may be a silicon die and may include a gate terminal 212, an emitter terminal 214, and a collector terminal), wherein each of the plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) is affixed to the die attachment region (figures 2, 3, 5 and 6, parts die attachment region of 208a, 208b and 210) at one of a plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) (paragraph [0029]; a first side 204a-1 of the switch 204a may be adjacent to and/or in contact with a top portion 208a-1 of the positive DC busbar 208a), wherein the one of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) for each of the plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) is selected to minimize a drain-source voltage overshoot (figure 4A, part minimize overshoot of Vce [Vds voltage in MOSFET application); through reduction in the parasitic inductance Ls) (paragraph [0024]; In some instances, the switch 110 may be a MOSFET-type switch and may include a drain (D) terminal, a source (S) terminal, and so on) of each of the plurality of power switch dies during switching (figures 2, 3, 5 and 6, parts 204a and 204b; through selecting the die locations of 204a and 204b that result in the reduction of the parasitic inductance, move the circuit to reduce the oscillation and therefore minimize the drain-source voltage overshoot of the power switches 204a/204b) (paragraphs [0025]-[0040]; The power loop 100-B electrical circuit, formed when one or more switches 110 are closed, may generate stray inductance 124, or a distributed parasitic inductance parameter intrinsic to one or more components of the power module portion 120, the DC link capacitor and busbars portion 122, and so on. The power loop 100-B stray inductance 124 may affect operation of the switches 110, such as, but not limited to, causing voltage overshoot during switching of the switches 110, thereby, resulting in a premature wear or failure of the switches 110… Thus, reducing the power loop stray inductance Ls may improve operation of the switches 204. Methods of reducing the stray inductance Ls include optimizing pin locations and overlaying the positive and negative DC busbar 208 terminals of each power module 202).
Regarding claim 2, Xu discloses everything claimed as applied above (see claim 1). Further, Xu discloses (see figures 1-6) the one of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) for each of the plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) is selected based at least in part on a parasitic inductance (figure 1B, part parasitic inductance 124 at 120) of each of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b), and wherein the parasitic inductance (figure 1B, part parasitic inductance 124 at 120) of each of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) is a parasitic inductance (figure 1B, part parasitic inductance 124 at 120) between each of the plurality of die locations (figures 1B, 2, 3, 5 and 6, parts die locations of 204a [110a] and 204b [110b]) and the terminal end of one of the plurality of DC bus bars (figures 1B, 2, 3, 5 and 6, parts terminal end of 208a, 208b and 210) (paragraph [0035]; Methods of reducing the stray inductance Ls include optimizing pin locations and overlaying the positive and negative DC busbar 208 terminals of each power module 202).
Regarding claim 3, Xu discloses everything claimed as applied above (see claim 2). Further, Xu discloses (see figures 1-6) the parasitic inductance (figure 1B, part parasitic inductance 124 at 120) of each of the plurality of die locations (figures 1B, 2, 3, 5 and 6, parts die locations of 204a [110a] and 204b [110b]) varies directly with a bus bar length (figures 2, 3, 5 and 6, parts length of 208a, 208b and 210) between each of the plurality of die locations (figures 1B, 2, 3, 5 and 6, parts die locations of 204a [110a] and 204b [110b]) and the terminal end (figures 1B, 2, 3, 5 and 6, parts terminal end of 208a, 208b and 210) (paragraph [0035]; Methods of reducing the stray inductance Ls include optimizing pin locations and overlaying the positive and negative DC busbar 208 terminals of each power module 202).
Regarding claim 11, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 12, claim 2 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 18, Xu discloses (see figures 1-6) a power inverter (figure 1A, part 106)for a vehicle (paragraph [0016]; hybrid electric vehicle (HEV)), the power inverter (figure 1A, part 106) comprising: a plurality of direct current (DC) bus bars (figures 2, 3, 5 and 6, parts 208a, 208b and 210) (paragraph [0027]; The DC busbars 208a, 208b and the AC busbar 210), wherein each of the plurality of DC bus bars (figures 2, 3, 5 and 6, parts 208a, 208b and 210) has a terminal end (figures 2, 3, 5 and 6, parts terminal end of 208a, 208b and 210) and a die attachment region (figures 2, 3, 5 and 6, parts die attachment region of 208a, 208b and 210); and a plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) (paragraph [0026]; The power module 202 may include a packaging structure 206 configured to receive a pair of switches 204, a pair of DC busbars 208, and an AC busbar 210… The switches 204 may be representative of a layout of the switches 110 described in reference to at least FIG. 1B. Each switch 204 may be a silicon die and may include a gate terminal 212, an emitter terminal 214, and a collector terminal), wherein each of the plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) is affixed to the die attachment region (figures 2, 3, 5 and 6, parts die attachment region of 208a, 208b and 210) at one of a plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) (paragraph [0029]; a first side 204a-1 of the switch 204a may be adjacent to and/or in contact with a top portion 208a-1 of the positive DC busbar 208a), wherein the one of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) for each of the plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) is selected to minimize a drain-source voltage overshoot (figure 4A, part minimize overshoot of Vce [Vds voltage in MOSFET application); through reduction in the parasitic inductance Ls) (paragraph [0024]; In some instances, the switch 110 may be a MOSFET-type switch and may include a drain (D) terminal, a source (S) terminal, and so on) of each of the plurality of power switch dies during switching (figures 2, 3, 5 and 6, parts 204a and 204b; through selecting the die locations of 204a and 204b that result in the reduction of the parasitic inductance, move the circuit to reduce the oscillation and therefore minimize the drain-source voltage overshoot of the power switches 204a/204b) (paragraphs [0025]-[0040]; The power loop 100-B electrical circuit, formed when one or more switches 110 are closed, may generate stray inductance 124, or a distributed parasitic inductance parameter intrinsic to one or more components of the power module portion 120, the DC link capacitor and busbars portion 122, and so on. The power loop 100-B stray inductance 124 may affect operation of the switches 110, such as, but not limited to, causing voltage overshoot during switching of the switches 110, thereby, resulting in a premature wear or failure of the switches 110… Thus, reducing the power loop stray inductance Ls may improve operation of the switches 204. Methods of reducing the stray inductance Ls include optimizing pin locations and overlaying the positive and negative DC busbar 208 terminals of each power module 202), wherein the one of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) for each of the plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) is selected based at least in part on a parasitic inductance (figure 1B, part parasitic inductance 124 at 120) of each of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b), and wherein the parasitic inductance (figure 1B, part parasitic inductance 124 at 120) of each of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) is a parasitic inductance (figure 1B, part parasitic inductance 124 at 120) between each of the plurality of die locations (figures 1B, 2, 3, 5 and 6, parts die locations of 204a [110a] and 204b [110b]) and the terminal end of one of the plurality of DC bus bars (figures 1B, 2, 3, 5 and 6, parts terminal end of 208a, 208b and 210) (paragraph [0035]; Methods of reducing the stray inductance Ls include optimizing pin locations and overlaying the positive and negative DC busbar 208 terminals of each power module 202).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-10, 13-17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (US 2019/0372063), hereinafter Xu, in view of Hasegawa et al. (US 2014/0184303), hereinafter Hasegawa.
Regarding claim 4, Xu discloses everything claimed as applied above (see claim 2). Further, Xu discloses (see figures 1-6) the one of the plurality of die locations (figures 1B, 2, 3, 5 and 6, parts die locations of 204a [110a] and 204b [110b]) for each of the plurality of power switch dies is selected (figures 2, 3, 5 and 6, parts 204a and 204b). However, Xu does not expressly disclose selected based at least in part on a threshold voltage of each of the plurality of power switch dies.
Hasegawa teaches (see figures 1-23) the one of the plurality of die locations (figure 2, part die locations of 1-6 and 7-12) for each of the plurality of power switch dies (figure 2, parts 1-6 and 7-12 at P1-P4) is selected based at least in part on a threshold voltage of each of the plurality of power switch dies (figure 2, parts threshold voltage of each of 1-6 and 7-12 at P1-P4) (figures 16 and 19, part Vth) (paragraphs [0006]-[0007]; This structure takes advantage of a difference in threshold voltage between the IGBT and the MOSFET… an ON threshold voltage for the IGBT is set higher than that of the MOSFET).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the plurality of die locations of Xu with the threshold voltage features as taught Hasegawa and obtain the one of the plurality of die locations for each of the plurality of power switch dies is selected based at least in part on a threshold voltage of each of the plurality of power switch dies, because it provides more efficient location in order to suppresses oscillation and reduce the size of the device (paragraphs [0008]-[0010]).
Regarding claim 5, Xu and Hasegawa teach everything claimed as applied above (see claim 4). Further, Xu discloses (see figures 1-6) a first power switch die of the plurality of power switch dies (figures 1B, 2, 3, 5 and 6, part 204a [110a]) is affixed at a first die location of the plurality of die locations (figures 1B, 2, 3, 5 and 6, parts die location of 204a [110a]), wherein the first power switch die has a first threshold voltage (figures 1B, 2, 3, 5 and 6, part first threshold voltage of 204a [110a]) and the first die location has a first parasitic inductance (figures 1B, 2, 3, 5 and 6, parts first parasitic inductance 124 of die location of 204a [110a]); and a second power switch die of the plurality of power switch dies (figures 1B, 2, 3, 5 and 6, part 204b [110b]) is affixed at a second die location of the plurality of die locations (figures 1B, 2, 3, 5 and 6, parts die location of 204b [110b]), wherein the second power switch die has a second threshold voltage (figures 1B, 2, 3, 5 and 6, part second threshold voltage of 204b [110b]) and the second die location has a second parasitic inductance (figures 1B, 2, 3, 5 and 6, parts second parasitic inductance 124 of die location of 204b [110b]), and the second parasitic inductance (figures 1B, 2, 3, 5 and 6, parts second parasitic inductance 124 of die location of 204b [110b]; more longer from 208b to 204b) is greater than the first parasitic inductance (figures 1B, 2, 3, 5 and 6, parts first parasitic inductance 124 of die location of 204a [110a]; more shorter from 208a to 204a). However, Xu does not expressly disclose the second threshold voltage is greater than the first threshold voltage.
Hasegawa teaches (see figures 1-23) a first power switch die of the plurality of power switch dies (figure 2, part 8 at P1) is affixed at a first die location of the plurality of die locations (figure 2, part die location of 8), wherein the first power switch die has a first threshold voltage (figure 2, part first threshold of 8 [MOSFET] at P1) and the first die location (figure 2, part die location of 8) has a first parasitic inductance (figure 2, part first parasitic inductance of die location at 8); and a second power switch die of the plurality of power switch dies (figure 2, part 4 at P2) is affixed at a second die location of the plurality of die locations (figure 2, part die location of 4), wherein the second power switch die (figure 2, part 4 at P2) has a second threshold voltage (figure 2, part second threshold of 4 at P2 [IGBT]) and the second die location (figure 2, part die location of 4) has a second parasitic inductance (figure 2, part second parasitic inductance of die location at 4), and wherein the second threshold voltage (figure 2, part second threshold of 4 at P2 [IGBT]) is greater than the first threshold voltage (figure 2, part first threshold of 8 [MOSFET] at P1) and the second parasitic inductance (figure 2, part second parasitic inductance of die location at 4; more longer from 4 to T5) is greater than the first parasitic inductance (figure 2, part first parasitic inductance of die location at 8; shorter from 8 to T1) (paragraphs [0006]-[0007]; This structure takes advantage of a difference in threshold voltage between the IGBT and the MOSFET… an ON threshold voltage for the IGBT is set higher than that of the MOSFET).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the plurality of die locations of Xu with the threshold voltage features as taught Hasegawa and obtain a first power switch die of the plurality of power switch dies is affixed at a first die location of the plurality of die locations, wherein the first power switch die has a first threshold voltage and the first die location has a first parasitic inductance; and a second power switch die of the plurality of power switch dies is affixed at a second die location of the plurality of die locations, wherein the second power switch die has a second threshold voltage and the second die location has a second parasitic inductance, and wherein the second threshold voltage is greater than the first threshold voltage and the second parasitic inductance is greater than the first parasitic inductance, because it provides more efficient location in order to suppresses oscillation and reduce the size of the device (paragraphs [0008]-[0010]).
Regarding claim 6, Xu and Hasegawa teach everything claimed as applied above (see claim 5). Further, Xu discloses (see figures 1-6) the plurality of DC bus bars (figures 2, 3, 5 and 6, parts 208a, 208b and 210) (paragraph [0027]; The DC busbars 208a, 208b and the AC busbar 210) includes: a positive DC bus bar (figures 2, 3, 5 and 6, parts 208a), wherein the positive DC bus bar (figures 2, 3, 5 and 6, parts 208a) has a positive terminal end (figures 2, 3, 5 and 6, parts positive terminal end DC+ at 208a) and a positive die attachment region (figures 2, 3, 5 and 6, parts positive die attachment region of 208a); and a negative DC bus bar (figures 2, 3, 5 and 6, parts 208b), wherein the negative DC bus bar (figures 2, 3, 5 and 6, parts 208b) has a negative terminal end (figures 2, 3, 5 and 6, part negative terminal end DC- at 208b) and a negative die attachment region (figures 2, 3, 5 and 6, parts negative die attachment region of 208b); and the plurality of power switch dies (figures 2, 3, 5 and 6, parts 204a and 204b) includes: a high-side power switch dies (figures 1B, 2, 3, 5 and 6, parts 204a[110a]), wherein each of high-side power switch dies (figures 1B, 2, 3, 5 and 6, parts 204a[110a]) is affixed to the positive die attachment region of the positive DC bus bar (figures 2, 3, 5 and 6, parts positive die attachment region of 208a) at one of the high-side die locations (figures 1B, 2, 3, 5 and 6, parts high-side die locations of 204a[110a]); and a low-side power switch dies (figures 1B, 2, 3, 5 and 6, parts 204b[110b]), wherein each of the low-side power switch dies (figures 1B, 2, 3, 5 and 6, parts 204b[110b]) is affixed to negative die attachment region of the negative DC bus bar (figures 2, 3, 5 and 6, parts negative die attachment region of 208b) at one of the low-side die locations (figures 1B, 2, 3, 5 and 6, part low-side die location of 204b[110b]). However, Xu does not expressly disclose a plurality of high-side power switch dies; and a plurality of low-side power switch dies.
Hasegawa teaches (see figures 1-23) the plurality of power switch dies (figure 2, parts 1-6 and 7-12 at P1-P4) includes: a plurality of high-side power switch dies (figures 1 and 2, parts 1-3 and 7-9 at P1), wherein each of the plurality of high-side power switch dies (figures 1 and 2, parts 1-3 and 7-9 at P1) is affixed to the positive die attachment region of the positive DC bus bar (figure 2, part T1) at one of a plurality of high-side die locations (figures 1 and 2, parts high-side die locations of 1-3 and 7-9 at P1); and a plurality of low-side power switch dies (figures 1 and 2, parts 4-6 and 10-12 at P2-P4), wherein each of the plurality of low-side power switch dies (figures 1 and 2, parts 4-6 and 10-12 at P2-P4) is affixed to negative die attachment region of the negative DC bus bar (figures 1 and 2, part T5) at one of a plurality of low-side die locations (figures 1 and 2, parts low-side die locations of 4-6 and 10-12 at P2-P4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the inverter of Xu with the inverter features as taught Hasegawa and obtain the plurality of DC bus bars includes: a positive DC bus bar, wherein the positive DC bus bar has a positive terminal end and a positive die attachment region; and a negative DC bus bar, wherein the negative DC bus bar has a negative terminal end and a negative die attachment region; and the plurality of power switch dies includes: a plurality of high-side power switch dies, wherein each of the plurality of high-side power switch dies is affixed to the positive die attachment region of the positive DC bus bar at one of a plurality of high-side die locations; and a plurality of low-side power switch dies, wherein each of the plurality of low-side power switch dies is affixed to negative die attachment region of the negative DC bus bar at one of a plurality of low-side die locations, because it provides more robust and efficient power conversion.
Regarding claim 7, Xu and Hasegawa teach everything claimed as applied above (see claim 6). Further, Xu discloses (see figures 1-6) the second die location (figures 1B, 2, 3, 5 and 6, parts high-side die locations of 204a[110a]) is one of the plurality of high-side die locations (figures 1B, 2, 3, 5 and 6, parts high-side die locations of 204a[110a]).
Regarding claim 8, Xu discloses everything claimed as applied above (see claim 2). Further, Xu discloses (see figures 1-6) the one of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) for each of the plurality of power switch dies is selected (figures 2, 3, 5 and 6, parts 204a and 204b). However, Xu does not expressly disclose selected based at least in part on a material type of each of the plurality of power switch dies.
Hasegawa teaches (see figures 1-23) the one of the plurality of die locations (figure 2, part die locations of 1-6 and 7-12) for each of the plurality of power switch dies (figure 2, parts 1-6 and 7-12 at P1-P4) is selected based at least in part on a material type of each of the plurality of power switch dies (figure 2, part die locations of 1-6 [IGBT; Si material] and 7-12 [MOSFET; SiC material]) (paragraph [0149]; only the MOSFET is a wide band-gap semiconductor device [SiC], whereas the IGBT is a reverse conducting IGBT or RC-IGBT shortly formed on a silicon substrate).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the plurality of die locations of Xu with the material type features as taught Hasegawa and obtain the one of the plurality of die locations for each of the plurality of power switch dies is selected based at least in part on a material type of each of the plurality of power switch dies, because it provides more efficient location in order to suppresses oscillation and reduce the size of the device (paragraphs [0008]-[0010]).
Regarding claim 9, Xu and Hasegawa teach everything claimed as applied above (see claim 8). Further, Xu discloses (see figures 1-6) the one of the plurality of die locations (figures 2, 3, 5 and 6, parts die locations of 204a and 204b) for each of the plurality of power switch dies is selected (figures 2, 3, 5 and 6, parts 204a and 204b). However, Xu does not expressly disclose a third power switch die of the plurality of power switch dies is affixed at a first die location of the plurality of die locations, wherein the third power switch die has a first material type and the first die location has a first parasitic inductance; and a fourth power switch die of the plurality of power switch dies is affixed at a second die location of the plurality of die locations, wherein the fourth power switch die has a second material type and the second die location has a second parasitic inductance, and wherein the second parasitic inductance is greater than the first parasitic inductance.
Hasegawa teaches (see figures 1-23) a third power switch die of the plurality of power switch dies (figure 2, part 11 [MOSFET] at P3) is affixed at a first die location of the plurality of die locations (figure 2, part die location of 11 [MOSFET]), wherein the third power switch die (figure 2, part 11 [MOSFET] at P3) has a first material type (figure 2, part 11 [MOSFET; SiC material] at P3) and the first die location has a first parasitic inductance (figure 2, part first parasitic inductance of the die location at 11 [MOSFET]) (paragraph [0149]; only the MOSFET is a wide band-gap semiconductor device [SiC], whereas the IGBT is a reverse conducting IGBT or RC-IGBT shortly formed on a silicon substrate); and a fourth power switch die of the plurality of power switch dies (figure 2, part 6 [IGBT] at P4) is affixed at a second die location of the plurality of die locations (figure 2, part die location of 6 [IGBT]), wherein the fourth power switch die (figure 2, part 6 [IGBT] at P4) has a second material type (figure 2, part 6 [IGBT; Si material] at P4) and the second die location (figure 2, part die location of 6 [IGBT]) has a second parasitic inductance (figure 2, part second parasitic inductance of the die location at 6 [IGBT]), and wherein the second parasitic inductance (figure 2, part second parasitic inductance of the die location at 6 [IGBT]; more longer from 6 to T5) is greater than the first parasitic inductance (figure 2, part first parasitic inductance of the die location at 11 [MOSFET]; more shorter from 11 to T5) (paragraph [0149]; only the MOSFET is a wide band-gap semiconductor device [SiC], whereas the IGBT is a reverse conducting IGBT or RC-IGBT shortly formed on a silicon substrate).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the plurality of die locations of Xu with the material type features as taught Hasegawa and obtain a third power switch die of the plurality of power switch dies is affixed at a first die location of the plurality of die locations, wherein the third power switch die has a first material type and the first die location has a first parasitic inductance; and a fourth power switch die of the plurality of power switch dies is affixed at a second die location of the plurality of die locations, wherein the fourth power switch die has a second material type and the second die location has a second parasitic inductance, and wherein the second parasitic inductance is greater than the first parasitic inductance, because it provides more efficient location in order to suppresses oscillation and reduce the size of the device (paragraphs [0008]-[0010]).
Regarding claim 10, Xu and Hasegawa teach everything claimed as applied above (see claim 9). However, Xu does not expressly disclose the first material type is silicon carbide and the second material type is silicon.
Hasegawa teaches (see figures 1-23) the first material type is silicon carbide (figure 2, part 11 [MOSFET; SiC material] at P3) and the second material type is silicon (figure 2, part 6 [IGBT; Si material] at P4) (paragraph [0149]; only the MOSFET is a wide band-gap semiconductor device [SiC], whereas the IGBT is a reverse conducting IGBT or RC-IGBT shortly formed on a silicon substrate).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the plurality of die locations of Xu with the material type features as taught Hasegawa and obtain the first material type is silicon carbide and the second material type is silicon, because it provides more efficient location in order to suppresses oscillation and reduce the size of the device (paragraphs [0008]-[0010]).
Regarding claim 13, claim 4 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 14, claim 5 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 15, claim 6 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 16, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 17, claims 9 and 10 have the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 19, claim 5 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 20, claim 9 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
Prosecution Insights