Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. The office acknowledges the receipt of the following and placed of record in the file: Amendment dated 8/13/2026.
2. Claims 19-33 for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 19-20, 22-23, 25 and 28-32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baileys et al. (“Baileys”), U.S. Patent Pub No. 2007/0174698 and Yuji Yokoya (“Yokoya”), U.S. Patent No. 6,199093.
Regarding Claim 19, Bailey teaches an operating method of a system on chip (SoC), the operating method comprising:
determining states of a first core and a second core included in the SoC [Para: 0049(detect status of “one or more VRM fails … detect these failures via status lines 504 and 524 and respond by activating control output lines 506 and 526 …” for microprocessors 586, 590 or other processors via status line 518 and 536, see para 0048)];
generating a first power gating signal to drive a first power gating switch (switch-566) which is arranged between the first core (microprocessor 586) and a first power rail that receives a first voltage (from VRM 550), according to the operating states of the first core and the second core [Para: 0048(“switches 566, 570, 572, and 574, respectively, coupling voltage from the VRMs to the individual processors” such as microprocessor 586) and 0052];
generating a second power gating signal to drive a second power gating switch (switch 570) which is arranged between the second core (microprocessor 588 or remaining processors) and a second power rail that receives a second voltage (from VRM 556), according to the operating states of the first core and the second core [Para: 0048(“switches 566, 570, 572, and 574, respectively, coupling voltage from the VRMs to the individual processors” such as microprocessor 588) and 0050]; and
generating a power control signal to drive a power switch (switch 568) which is arranged between the first power rail and the second power rail [Fig-5(switch 568 coupling power rail coupling processor 586 rail with processor 588 rail)], based on at least one of an operating frequency, an operating voltage (voltage from VRM 556) or a workload of an active core of the first core and the second core [Fig-5], so that the active core is connected to both the first power rail and the second power rail through one of the first power gating switch and the second power gating switch, which is connected to the active core, and the power switch [Para: 0049(as “route power from VRM 556 to microprocessor 586 … closing switch 568”)].
Bailey does not disclose clearly determining operating states of a first core and a second core.
specifically determining the operating states comprises determining by a control logic included in the SoC, whether each of the first core and the second core is in active an active state or and idle state based on task schedules of the first core and the second core.
In the same field of endeavor, (e.g., processor allocating method for task scheduling in a multiprocessor system), Yokoya teaches wherein determining operating states comprises determining by a control logic included in the SoC, whether each of the first core and the second core is in active an active state (cores that are “already been allocated”) or an idle state (cores that are not yest been allocated”) based on task schedules of the first core and the second core [col-2 lines: lines43-53(a logic that determines “task schedule means for allocating such a processor to a task to which the processor has not yet been allocated, among said plural tasks … to be allocated and another processor already allocated …”) and col-3 lines: 57-67(a logic to determine “task schedule means for obtaining such a processor from said processor communication table … the processor has not yet been allocated, … and another processor already allocated”)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Bailey’s teachings of determining a state of a fist core and a second core and generating a power gating signal to drive a switch with Yokoya’s teachings of determining operating states of a first core and a second core would allow Bailey to schedule cores for their respective tasks based on a table indicating allocation state which intern reduce communication latency [Yokoya, col-1 lines: 53-67] and improve performance.
Regarding Claim 20, Bailey teaches wherein the determining of the operating states comprises: scheduling tasks of the first core and the second core [Para: 0035(“processing data such as pipelining time-sharing …”)]; and determining the operating states of the first core and the second core based on scheduled tasks of the first core and the second core [Para: 0037].
Regarding Claim 22, Bailey teaches wherein the generating of the power control signal comprises: disabling the power control signal in response to the first core and the second core being in an active state or an idle state [Para: 0010, 0034 and 0044].
Regarding Claim 23, Bailey teaches generating a voltage control signal based on the at least one of the operating frequency, the operating voltage [Para: 0007, 0009, 0048] or the workload of the active core of the first core and the second core.
Regarding Claim 25, Baileys teaches wherein the generating of the first power gating signal comprises:
enabling the first power gating signal to turn on the first power gating switch to electrically connect the first power rail with the first core, in response to the first core being in an active state [Para: (“switches 566, 570, 572, and 574, respectively, coupling voltage from the VRMs to the individual processors” such as microprocessor 586) and 0052, and
wherein the generating of the second power gating signal comprises:
disabling the second power gating signal to turn off the second power gating switch to electrically insulate the second power rail from the second core, in response to the first core being in the active state and the second core being in the idle state [Para: 0042(when microprocessor (380) “tri-states its input-output lines … may isolate microprocessor 380”)] and 0049(isolate VRM)].
Regarding Claim 28, Baileys teaches wherein the generating of the first power gating signal comprises: enabling the first power gating signal to turn on the first power gating switch to electrically connect the first power rail with the first core, in response to both of the first core and the second core being in an active state, and wherein the generating of the second power gating signal comprises: enabling the second power gating signal to turn on the second power gating switch to electrically connect the second power rail with the second core, in response to both of the first core and the second core being in the active state [Para: 0048].
Regarding Claim 29 and 31, Baileys teaches disabling the power control signal to turn off the power switch, in response to both of the first core and the second core being in the active state [Para: 0032(“switching module 114 to uncouple … isolated from other output … normal mode …”) and 0049(as open switches 566, 572” or other switches (such as 570) to isolate VRMs)].
Regarding Claim 30, Baileys teaches wherein the generating of the first power gating signal comprises: disabling the first power gating signal to turn off the first power gating switch to electrically insulate the first power rail from the first core, in response to both of the first core and the second core being in an idle state, and wherein the generating of the second power gating signal comprises: disabling the second power gating signal to turn off the second power gating switch to electrically insulate the second power rail from the second core, in response to both of the first core and the second core being in the idle state [Para: 0042(when microprocessor (380) “tri-states its input-output lines … may isolate microprocessor 380”)].
Regarding Claim 32, Baileys teaches wherein the generating of the first power gating signal comprises: generating the first power gating signal based on at least one of the operating states, operating frequencies, or workloads of the first core and the second core [Para: 0048(“switches 566, 570, 572, and 574, respectively, coupling voltage from the VRMs to the individual processors” such as microprocessor 586) and 0052], and wherein the generating of the second power gating signal comprises: generating the second power gating signal based on at least one of the operating states, the operating frequencies, or the workloads of the first core and the second core [Para: 0048(“switches 566, 570, 572, and 574, respectively, coupling voltage from the VRMs to the individual processors” such as microprocessor 588) and 0052].
4. Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bowles et al. (“Bowles”), U.S. Patent No. 10,014,869 and Yokoya as set forth above.
Regarding Claim 33, Bowles teaches an operating method of an electronic device including a system on chip (SoC) and a power management integrated circuit (PMIC) [Fig-1C], the operating method comprising:
determining states of a first core and a second core included in the SoC, by the SoC [col-3 lines: 47-54(determining a state for “controlling the power supplied to IC core … particular supply or rail voltage and clock signal with particular clock frequency”)];
monitoring an operating frequency of an active core of the first core and the second core, by the SoC (monitor for DCVS request and change “frequency control signals M/N1 to M/Nn to provide the requested power to cores”);
generating a voltage control signal based on the operating frequency of the active core, by the SoC (“MPU 110 generates regulator control signal RCS1 to RCSn …” upon receiving DCVS request);
transmitting the voltage control signal from the SoC to the PMIC; generating a first voltage and a second voltage based on the voltage control signal, by the PMIC; and [col-3 line: 55 – col-4 line: 45 (“PMU 110 configured to receive DCVS requests … PMU 110 generates regulator control signals RCS.sub.1 to RCS.sub.n …generate rail voltages VDD.sub.1 to VDD.sub.n”)];
providing the first voltage through a first power rail, from the PMIC to the SoC (as “in turn, generate rail voltages VDD1 to VDDn” for core 1); and
providing the second voltage through a second power rail, from the PMIC to the SoC [col-4 lines: 23-45 (as “generate rail voltages VDD1 to VDDn” for core n)].
Bowles does not disclose expressly determining operating states of cores and wherein the determining of the operating states comprises determining by a control logic included in the SoC, whether each of the first core and the second core is in active an active state or an idle state based on task schedules of the first core and the second core.
In the same field of endeavor, (e.g., processor allocating method for task scheduling in a multiprocessor system), Yokoya teaches determining operating states of cores and wherein the determining of the operating states comprises determining by a control logic included in the SoC, whether each of the first core and the second core is in active an active state (cores that are “already been allocated”) or and idle state (cores that are not yest been allocated”) based on task schedules of the first core and the second core [col-2 lines: lines43-53(a logic that determines “task schedule means for allocating such a processor to a task to which the processor has not yet been allocated, among said plural tasks … to be allocated and another processor already allocated …”) and col-3 lines: 57-67(a logic to determine “task schedule means for obtaining such a processor from said processor communication table … the processor has not yet been allocated, … and another processor already allocated”)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Bowles’s teachings of determining a state of a fist core and a second core and monitoring active frequency of an active core with Yokoya’s teachings of determining operating states of a first core and a second core would allow Bailey to schedule cores for their respective tasks based on a table indicating allocation state which intern reduce communication latency [Yokoya, col-1 lines: 53-67] and improve performance.
5. Claim(s) 21 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bailey and Yokoya applied to claim 19 (hereinafter “Bailey-Yokoya”) and Bowles as stated above.
Regarding Claim 24, Bailey-Yokoya teaches all limitations of claim 24 as described rejecting Claim 23 above. Bailey-Yokoya does not disclose expressly wherein the generating of the power control signal and the generating of the voltage control signal are substantially simultaneously performed.
In the same field of endeavor (e.g., clock generation and ramp control circuit), Bowles teaches wherein generation of the power control signal (DCVS request) and the generation of the voltage control signal (RCS signal) are substantially simultaneously performed [col-4 lines: 1-45 (PMU 110 configured to receive DCVS requests … PMU 110 generates regulator control signals RCS.sub.1 to RCS.sub.n … in turn, generate rail voltages VDD.sub.1 to VDD.sub.n based on the control signals RCS1 to RCSn”)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Bailey-Yokoya’s teachings of generation of the power control signal to drive a power switch with Bowles’s teachings of generation of power control signal and voltage control signal are substantially simultaneously performed would allow Bailey to mitigate voltage droop in fast frequency-voltage changing environment [Bowles, col-1 lines: 43-50].
Regarding Claim 21, Bailey-Yokoya teaches wherein the determining of the operating states comprises: scheduling tasks of the first core and the second core [Bailey, Para: 0035(processing data such as pipelining time-sharing …”)]. One of ordinary skill in the art would look at a task schedule to determine operating states of the first core and the second core for the purpose of plan execution of tasks in order to avoid processor pipeline congestion and performance degradation.
6. Claim(s) 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bailey-Yokoya and Coutelou et al. (“Coutelou”), U.S. Patent Pub No. 2011/0196629.
Regarding Claims 26 and 27, Bailey-Yokoya teaches wherein the generating of the power control signal comprises: enabling the power control signal to turn on the power switch (568) to connect the first power gating switch to both the first power rail and the second power rail, in response to the first core being in the active state and the second core being in the active/idle state [Bailey, Para: 0049(as “route power from VRM 556 to microprocessor 586 … closing switch 568”)]. Bailey-Yokoya does not disclose expressly turn-on the power switch to connect power gating switch in response to operating frequency of the first core being higher than a reference frequency or the operating voltage being greater than the first voltage.
In the same field of endeavor (e.g., electric power control and metering device), Coutelou teaches turn-on the power switch to connect power gating switch in response to operating frequency of the first core being higher than a reference frequency or the operating voltage being greater than a reference/the first voltage [Para: 0070(When the voltage of the capacitor exceeds a predefined threshold Svc, turn-on of a switch is actuated in a step 61 in order to supply of a processing power)].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Bailey-Yokoya’s teachings of generation of the power control signal to drive a power switch and Coutelou’s teachings of turn-on the power switch to connect power gating switch in response to the operating voltage being greater/below than a reference voltage for the purpose of dynamically turning on/off a switch to connect or disconnect a power rail in order to optimize power-performance balance without any performance degradation.
Response to Arguments
7. Applicant’s arguments, filed on 8/13/26, with respect to the rejection(s) of claim(s) 19 and 33 under Claim Rejections - 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Bailey-Yokoya and Bowles-Yokoya.
Conclusion
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/MOHAMMED H REHMAN/Primary Examiner, Art Unit 2176
